89     assert(Target->isReg());  in SDWAOperand()
90     assert(Replaced->isReg());  in SDWAOperand()
246   assert(To.isReg() && From.isReg());  in copyRegOperand()
258   return LHS.isReg() &&  in isSameReg()
259          RHS.isReg() &&  in isSameReg()
266   if (!Reg->isReg() || !Reg->isDef())  in findSingleRegUse()
288   if (!Reg->isReg())  in findSingleRegDef()
296     if (DefMO.isReg() && DefMO.getReg() == Reg->getReg())  in findSingleRegDef()
347   assert(Src && (Src->isReg() || Src->isImm()));  in convertToSDWA()
389     assert(Src && Src->isReg());  in convertToSDWA()
446          Operand->isReg() &&  in convertToSDWA()
468     if (!MO.isReg())  in convertToSDWA()
499   if (Op.isReg()) {  in foldToImm()
697         if (!Op1 || !Op1->isReg() || !Op2 || !Op2->isReg())  in matchSDWAOperand()
807     assert(OrDst && OrDst->isReg());  in matchSDWAOperand()
966     if (!Src0->isReg() && !Src0->isImm())  in isConvertibleToSDWA()
971     if (!Src1->isReg() && !Src1->isImm())  in isConvertibleToSDWA()
1168     if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg())))  in legalizeScalarOperands()
1176     if (ST.hasSDWAScalar() && ConstantBusCount == 0 && Op.isReg() &&  in legalizeScalarOperands()
1187     else if (Op.isReg())  in legalizeScalarOperands()