341     bool isReg() const { return Kind == CV_Register; }  in isReg()  function in __anon2e2dc8d40111::CountValue
345       assert(isReg() && "Wrong CountValue accessor");  in getReg()
350       assert(isReg() && "Wrong CountValue accessor");  in getSubReg()
360       if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }  in print()
677   if (Op1.isReg()) {  in getLoopTripCount()
697   if (InitialValue->isReg()) {  in getLoopTripCount()
707   if (EndValue->isReg()) {  in getLoopTripCount()
737   if (Start->isReg()) {  in computeCount()
743   if (End->isReg()) {  in computeCount()
750   if (!Start->isReg() && !Start->isImm())  in computeCount()
752   if (!End->isReg() && !End->isImm())  in computeCount()
850   bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm)  in computeCount()
851   bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg)  in computeCount()
888   if (Start->isReg()) {  in computeCount()
1036     if (!MO.isReg() || !MO.isDef())  in isDead()
1056       if (!OPO.isReg() || !OPO.isDef())  in isDead()
1090       if (!MO.isReg() || !MO.isDef())  in removeIfDead()
1205   if (TripCount->isReg()) {  in convertToHardwareLoop()
1241   if (TripCount->isReg()) {  in convertToHardwareLoop()
1339       if (MO.isReg() && MO.isUse()) {  in orderBumpCompare()
1413   if (!InitVal->isReg())  in loopCountMayWrapOrUnderFlow()
1497   if (!MO.isReg())  in checkForImmediate()
1578   assert(MO.isReg());  in setImmediate()
1686   if (!Cond[CSz-1].isReg())  in fixupInductionVariable()
1704     if (MO.isReg()) {  in fixupInductionVariable()
1753           if (MO.isReg() && MO.getReg() == RB.first) {  in fixupInductionVariable()
1761           } else if (MO.isReg()) {  in fixupInductionVariable()
1820         if (MO.isReg() && MO.getReg() == RB.first) {  in fixupInductionVariable()