Lines Matching refs:isReg
47 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding()
64 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
77 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
90 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
102 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register"); in getVSRpEvenEncoding()
112 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
125 assert(!MO.isReg() && "Not expecting a register for this operand."); in getImm34Encoding()
155 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
173 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
191 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
216 assert(RegMO.isReg() && "Base address must be a register."); in getMemRIHashEncoding()
321 assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register."); in getMemRI34Encoding()
334 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
349 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
364 assert(MI.getOperand(OpNo+1).isReg()); in getSPE2DisEncoding()
377 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in getTLSRegEncoding()
434 if (MO.isReg()) { in getMachineOpValue()