151     if (MO.isReg())  in removeRegOperandsFromUseLists()
157     if (MO.isReg())  in addRegOperandsToUseLists()
204   bool isImpReg = Op.isReg() && Op.isImplicit();  in addOperand()
206     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {  in addOperand()
248   if (NewMO->isReg()) {  in addOperand()
283     if (Operands[i].isReg())  in removeOperand()
288   if (MRI && Operands[OpNo].isReg())  in removeOperand()
598     if (!MO.isReg()) {  in isIdenticalTo()
691     if (MO.isReg() && MO.isImplicit())  in getNumExplicitOperands()
705     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())  in getNumExplicitDefs()
844   if (!getOperand(OpIdx).isReg())  in getRegClassConstraint()
895   if (!MO.isReg() || MO.getReg() != Reg)  in getRegClassConstraintEffectForVRegImpl()
906   assert(MO.isReg() &&  in getRegClassConstraintEffect()
936     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)  in hasRegisterImplicitUseOperand()
949     if (!MO.isReg() || !MO.isUse())  in findRegisterUseOperandIdx()
973     if (!MO.isReg() || MO.getReg() != Reg)  in readsWritesVirtualRegister()
1003     if (!MO.isReg() || !MO.isDef())  in findRegisterDefOperandIdx()
1095       if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)  in findTiedOperandIdx()
1109       while (!getOperand(CurUseIdx).isReg())  in findTiedOperandIdx()
1157     if (MO.isReg() && MO.isUse())  in clearKillInfo()
1169       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1175       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1424     if (!MO.isReg() || MO.isUse())  in allDefsAreDead()
1438     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())  in copyImplicitOps()
1448     if (!Operand.isReg() || Operand.isDef())  in hasComplexRegisterTies()
1462   if (!Op.isReg())  in getTypeToPrint()
1502     if (!MO.isReg() || MO.isDef())  in dumprImpl()
1557     if (MO.isReg() && MO.isTied() && !MO.isDef())  in print()
1567     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())  in print()
1832     if (!MO.isReg() || !MO.isUse() || MO.isUndef())  in addRegisterKilled()
1893     if (!MO.isReg() || !MO.isUse() || !MO.isKill())  in clearRegisterKills()
1911     if (!MO.isReg() || !MO.isDef())  in addRegisterDead()
1956     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)  in clearRegisterDeads()
1964     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)  in setRegisterDefReadUndef()
1978       if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&  in addRegisterDefined()
1996     if (!MO.isReg() || !MO.isDef()) continue;  in setPhysRegsDeadExcept()
2020     if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))  in getHashValue()
2074   if (MO.isReg())  in BuildMI()
2099     if (MO.isReg())  in BuildMI()
2186       if (Op.isReg() && Op.getReg() == SpillReg)  in buildDbgValueForSpill()
2228   if (!MI.getOperand(0).isReg())  in collectDebugValues()
2245   if (!getOperand(0).isReg())  in changeDebugValuesDefReg()