179       if (MI->getOperand(1).isReg())  in isFixedInstr()
184       if (MI->getOperand(0).isReg())  in isFixedInstr()
211     if (!Op.isReg())  in isFixedInstr()
259         if (&MO == &Op || !MO.isReg() || MO.getSubReg())  in partitionRegisters()
442           if (Op.isReg() && Part.count(Op.getReg()))  in isProfitable()
499   assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch");  in collectIndRegsForLoop()
596     if (!Op.isReg()) {  in createHalfInstr()
700   assert(Op0.isReg() && Op1.isImm());  in splitImmediate()
728   assert(Op0.isReg());  in splitCombine()
736   if (!Op1.isReg()) {  in splitCombine()
744   if (!Op2.isReg()) {  in splitCombine()
757   assert(Op0.isReg() && Op1.isReg());  in splitExt()
780   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());  in splitShift()
905   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());  in splitAslOr()
1076     if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())  in replaceSubregUses()
1101     if (!Op.isReg() || !Op.isUse())  in collapseRegPairs()