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Searched refs:VecVT (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp120 auto VecVT = EVT::getVectorVT(Context, IntVT, 3); in TEST_F() local
122 auto Vec = DAG->getConstant(0, Loc, VecVT); in TEST_F()
159 auto Vec = DAG->getConstant(1, Loc, VecVT); in TEST_F()
173 auto Vec = DAG->getConstant(1, Loc, VecVT); in TEST_F()
279 SDValue Op = DAG->getConstant(1, Loc, VecVT); in TEST_F()
300 SDValue Val1 = DAG->getConstant(1, Loc, VecVT); in TEST_F()
301 SDValue Val2 = DAG->getConstant(3, Loc, VecVT); in TEST_F()
323 SDValue Op = DAG->getConstant(1, Loc, VecVT); in TEST_F()
367 SDValue Op = DAG->getConstant(1, Loc, VecVT); in TEST_F()
400 SDValue Op = DAG->getConstant(1, Loc, VecVT); in TEST_F()
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H A DSelectionDAGAddressAnalysisTest.cpp104 auto VecVT = EVT::getVectorVT(Context, Int8VT, 4); in TEST_F() local
105 SDValue FIPtr = DAG->CreateStackTemporary(VecVT); in TEST_F()
109 SDValue Value = DAG->getConstant(0, Loc, VecVT); in TEST_F()
127 auto VecVT = EVT::getVectorVT(Context, Int8VT, 4); in TEST_F() local
128 SDValue FIPtr = DAG->CreateStackTemporary(VecVT); in TEST_F()
132 SDValue Value = DAG->getConstant(0, Loc, VecVT); in TEST_F()
153 auto VecVT = EVT::getVectorVT(Context, Int8VT, 4); in TEST_F() local
156 SDValue FIPtr = DAG->CreateStackTemporary(VecVT); in TEST_F()
188 SDValue FIPtr = DAG->CreateStackTemporary(VecVT); in TEST_F()
215 SDValue FIPtr = DAG->CreateStackTemporary(VecVT); in TEST_F()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1544 VecVT = VecVT.getHalfNumVectorElementsVT(); in decomposeSubvectorInsertExtractToSubRegs()
1773 return getDefaultVLOps(VecVT, VecVT, DL, DAG, Subtarget); in getDefaultScalableVLOps()
4190 return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT), in lowerSPLAT_VECTOR_PARTS()
4198 return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT), Lo, in lowerSPLAT_VECTOR_PARTS()
5399 if (!VecVT.isInteger()) in lowerVPREDUCE()
5433 VecVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorMinNumElements() / 8, in lowerINSERT_SUBVECTOR()
5520 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerINSERT_SUBVECTOR()
5585 VecVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorMinNumElements() / 8, in lowerEXTRACT_SUBVECTOR()
5654 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerEXTRACT_SUBVECTOR()
5822 DAG.getNode(RISCVISD::VSLIDEDOWN_VL, DL, VecVT, DAG.getUNDEF(VecVT), V1, in lowerVECTOR_SPLICE()
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H A DRISCVISelLowering.h580 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp373 EVT VecVT = N->getValueType(0); in ExpandOp_BUILD_VECTOR() local
374 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_BUILD_VECTOR()
379 assert(OldVT == VecVT.getVectorElementType() && in ExpandOp_BUILD_VECTOR()
400 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_BUILD_VECTOR()
411 EVT VecVT = N->getValueType(0); in ExpandOp_INSERT_VECTOR_ELT() local
412 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_INSERT_VECTOR_ELT()
419 assert(OldEVT == VecVT.getVectorElementType() && in ExpandOp_INSERT_VECTOR_ELT()
442 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp1379 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR() local
1634 return DAG.getBuildVector(VecVT, dl, Scalars); in UnrollVectorOp_StrictFP()
1707 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_VECTOR_ELT() local
1708 EVT EltVT = VecVT.getVectorElementType(); in SplitVecRes_INSERT_VECTOR_ELT()
1709 if (VecVT.getScalarSizeInBits() < 8) { in SplitVecRes_INSERT_VECTOR_ELT()
2854 EVT VecVT = VecOp.getValueType(); in SplitVecOp_VECREDUCE() local
2876 EVT VecVT = VecOp.getValueType(); in SplitVecOp_VECREDUCE_SEQ() local
2899 EVT VecVT = VecOp.getValueType(); in SplitVecOp_VP_REDUCE() local
3030 EVT VecVT = Vec.getValueType(); in SplitVecOp_EXTRACT_VECTOR_ELT() local
3054 EVT EltVT = VecVT.getVectorElementType(); in SplitVecOp_EXTRACT_VECTOR_ELT()
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H A DLegalizeDAG.cpp1397 EVT VecVT = Vec.getValueType(); in ExpandExtractFromVectorThroughStack() local
1401 StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandExtractFromVectorThroughStack()
1413 StackPtr = TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, in ExpandExtractFromVectorThroughStack()
1418 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); in ExpandExtractFromVectorThroughStack()
1420 MachinePointerInfo(), VecVT.getVectorElementType(), in ExpandExtractFromVectorThroughStack()
1446 EVT VecVT = Vec.getValueType(); in ExpandInsertToVectorThroughStack() local
1448 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandInsertToVectorThroughStack()
1458 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in ExpandInsertToVectorThroughStack()
H A DTargetLowering.cpp844 EVT VecVT = Vec.getValueType(); in SimplifyMultipleUseDemandedBits() local
845 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && in SimplifyMultipleUseDemandedBits()
1170 EVT VecVT = Vec.getValueType(); in SimplifyDemandedBits() local
1175 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) { in SimplifyDemandedBits()
8682 EVT VecVT, const SDLoc &dl, in clampDynamicVectorIndex() argument
8684 assert(!(SubEC.isScalable() && VecVT.isFixedLengthVector()) && in clampDynamicVectorIndex()
8687 unsigned NElts = VecVT.getVectorMinNumElements(); in clampDynamicVectorIndex()
8691 if (VecVT.isScalableVector() && !SubEC.isScalable()) { in clampDynamicVectorIndex()
8719 DAG, VecPtr, VecVT, in getVectorElementPointer()
8732 EVT EltVT = VecVT.getVectorElementType(); in getVectorSubVecPointer()
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H A DDAGCombiner.cpp19764 EVT VecVT = VecOp.getValueType(); in visitEXTRACT_VECTOR_ELT() local
19799 if (IndexC && VecVT.isFixedLengthVector() && in visitEXTRACT_VECTOR_ELT()
19806 TLI.isTypeLegal(VecVT) && in visitEXTRACT_VECTOR_ELT()
19809 VecVT.isFixedLengthVector()) && in visitEXTRACT_VECTOR_ELT()
19827 if (VecVT.isScalableVector()) in visitEXTRACT_VECTOR_ELT()
19833 unsigned NumElts = VecVT.getVectorNumElements(); in visitEXTRACT_VECTOR_ELT()
19952 EVT ExtVT = VecVT.getVectorElementType(); in visitEXTRACT_VECTOR_ELT()
20173 if (!isTypeLegal(VecVT) || in reduceBuildVecExtToExtBuildVec()
20179 SDValue BV = DAG.getBuildVector(VecVT, DL, Ops); in reduceBuildVecExtToExtBuildVec()
21314 EVT VecVT = BinOp.getValueType(); in narrowInsertExtractVectorBinOp() local
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H A DSelectionDAG.cpp3629 EVT VecVT = InVec.getValueType(); in computeKnownBits() local
3631 if (VecVT.isScalableVector()) in computeKnownBits()
3633 const unsigned EltBitWidth = VecVT.getScalarSizeInBits(); in computeKnownBits()
3634 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in computeKnownBits()
4332 EVT VecVT = InVec.getValueType(); in ComputeNumSignBits() local
4334 if (VecVT.isScalableVector()) in ComputeNumSignBits()
4338 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in ComputeNumSignBits()
11157 EVT VecVT = EVT::getVectorVT(*getContext(), EltVT, ResNE); in UnrollVectorOp() local
11158 return getBuildVector(VecVT, dl, Scalars); in UnrollVectorOp()
11346 assert(VecVT.getVectorElementCount().isKnownEven() && in SplitEVL()
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H A DLegalizeFloatTypes.cpp2363 EVT VecVT = Vec->getValueType(0); in PromoteFloatRes_EXTRACT_VECTOR_ELT() local
2364 EVT EltVT = VecVT.getVectorElementType(); in PromoteFloatRes_EXTRACT_VECTOR_ELT()
2368 switch (getTypeAction(VecVT)) { in PromoteFloatRes_EXTRACT_VECTOR_ELT()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5538 EVT VecVT = Op0.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
6144 if (Op.getValueType() != VecVT) { in combineExtract()
6164 EVT VecVT = Vec.getValueType(); in combineTruncateExtract() local
6165 if (canTreatAsByteVector(VecVT)) { in combineTruncateExtract()
6579 EVT VecVT = Op.getValueType(); in combineEXTRACT_VECTOR_ELT() local
6595 EVT VecVT = Op0.getValueType(); in combineEXTRACT_VECTOR_ELT() local
6848 EVT VecVT = N->getValueType(0); in combineBSWAP() local
6850 if (VecVT != Vec.getValueType()) { in combineBSWAP()
6877 EVT VecVT = N->getValueType(0); in combineBSWAP() local
6878 if (VecVT != Op0.getValueType()) { in combineBSWAP()
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H A DSystemZISelLowering.h693 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
780 MVT VecVT; member
H A DSystemZISelDAGToDAG.cpp1155 assert(VCI.VecVT.getSizeInBits() == 128 && "Expected a vector type"); in loadVectorConstant()
1161 SDValue Op = CurDAG->getNode(VCI.Opcode, DL, VCI.VecVT, Ops); in loadVectorConstant()
1163 if (VCI.VecVT == VT.getSimpleVT()) in loadVectorConstant()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4191 if (VecVT.isFloatingPoint()) { in getVCmpInst()
4214 if (VecVT == MVT::v4f32) in getVCmpInst()
4216 else if (VecVT == MVT::v2f64) in getVCmpInst()
4221 if (VecVT == MVT::v4f32) in getVCmpInst()
4223 else if (VecVT == MVT::v2f64) in getVCmpInst()
4228 if (VecVT == MVT::v4f32) in getVCmpInst()
4230 else if (VecVT == MVT::v2f64) in getVCmpInst()
4258 if (VecVT == MVT::v16i8) in getVCmpInst()
4270 if (VecVT == MVT::v16i8) in getVCmpInst()
4282 if (VecVT == MVT::v16i8) in getVCmpInst()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3972 VecVT = MVT::v8f32; in forwardMustTailParameters()
3974 VecVT = MVT::v4f32; in forwardMustTailParameters()
19770 if (VecVT.is256BitVector() || VecVT.is512BitVector()) { in LowerEXTRACT_VECTOR_ELT()
19846 Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask); in LowerEXTRACT_VECTOR_ELT()
19862 Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask); in LowerEXTRACT_VECTOR_ELT()
43494 if ((VecVT.is256BitVector() || VecVT.is512BitVector()) && in combineExtractWithShuffle()
43505 if ((VecVT == MVT::v4i32 || VecVT == MVT::v2i64) && in combineExtractWithShuffle()
43745 SDValue Lo = getUnpackl(DAG, DL, VecVT, Rdx, DAG.getUNDEF(VecVT)); in combineArithReduction()
43746 SDValue Hi = getUnpackh(DAG, DL, VecVT, Rdx, DAG.getUNDEF(VecVT)); in combineArithReduction()
43774 if (VecVT == MVT::v4i8 || VecVT == MVT::v8i8) { in combineArithReduction()
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H A DX86ISelDAGToDAG.cpp422 MVT VecVT = N->getOperand(0).getSimpleValueType(); in getExtractVEXTRACTImmediate() local
423 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getExtractVEXTRACTImmediate()
430 MVT VecVT = N->getSimpleValueType(0); in getInsertVINSERTImmediate() local
431 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getInsertVINSERTImmediate()
438 MVT VecVT = N->getSimpleValueType(0); in getPermuteVINSERTCommutedImmediate() local
1190 MVT VecVT = VT == MVT::f64 ? MVT::v2f64 in PreprocessISelDAG() local
1195 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1197 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1202 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG()
1214 Res = CurDAG->getNode(ISD::BITCAST, dl, VecVT, Res); in PreprocessISelDAG()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5655 EVT VecVT = Vec.getValueType(); in lowerINSERT_SUBVECTOR() local
5657 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_SUBVECTOR()
5676 EVT VecVT = Vec.getValueType(); in lowerINSERT_VECTOR_ELT() local
5677 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_VECTOR_ELT()
5678 unsigned VecSize = VecVT.getSizeInBits(); in lowerINSERT_VECTOR_ELT()
5757 EVT VecVT = Vec.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
5758 unsigned VecSize = VecVT.getSizeInBits(); in lowerEXTRACT_VECTOR_ELT()
7948 EVT VecVT = in handleD16VData() local
10626 EVT VecVT = Vec.getValueType(); in shouldExpandVectorDynExt() local
10640 EVT VecVT = Vec.getValueType(); in performExtractVectorEltCombine() local
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H A DAMDGPUISelLowering.h195 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
H A DR600ISelLowering.cpp622 EVT VecVT = Vector.getValueType(); in vectorToVerticalVector() local
623 EVT EltVT = VecVT.getVectorElementType(); in vectorToVerticalVector()
626 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) { in vectorToVerticalVector()
631 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6179 EVT VecVT = EVT::getVectorVT( in CombineVMOVDRRCandidateWithVecOp() local
8939 EVT VecVT = VecIn.getValueType(); in LowerINSERT_VECTOR_ELT() local
13141 if (!VecVT.isPow2VectorType() || VecVT.getVectorNumElements() == 1) in PerformVQDMULHCombine()
13153 if (VecVT.getSizeInBits() < 128) { in PerformVQDMULHCombine()
15105 if (!TLI.isTypeLegal(VecVT)) in PerformARMBUILD_VECTORCombine()
15113 SDValue Vec = DAG.getUNDEF(VecVT); in PerformARMBUILD_VECTORCombine()
15280 EVT VecVT = Op0.getValueType(); in PerformExtractEltToVMOVRRD() local
15283 if (VecVT.getVectorNumElements() != 4) in PerformExtractEltToVMOVRRD()
15444 EVT VecVT = Vec.getValueType(); in PerformInsertSubvectorCombine() local
15448 if (!VecVT.isFixedLengthVector() || in PerformInsertSubvectorCombine()
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H A DARMISelDAGToDAG.cpp4321 EVT VecVT = N->getValueType(0); in Select() local
4322 EVT EltVT = VecVT.getVectorElementType(); in Select()
4323 unsigned NumElts = VecVT.getVectorNumElements(); in Select()
4327 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4333 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4338 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1), in Select()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3044 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const { in aggressivelyPreferBuildVectorSources() argument
4820 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
4828 SDValue getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp392 EVT VecVT = VecOp.getValueType(); in shouldScalarizeBinop() local
393 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT)) in shouldScalarizeBinop()
398 EVT ScalarVT = VecVT.getScalarType(); in shouldScalarizeBinop()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp7752 EVT VecVT; in LowerFCOPYSIGN() local
7756 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In1); in LowerFCOPYSIGN()
7758 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In2); in LowerFCOPYSIGN()
7760 VecVal1 = BitCast(VecVT, In1, DAG); in LowerFCOPYSIGN()
7761 VecVal2 = BitCast(VecVT, In2, DAG); in LowerFCOPYSIGN()
7765 VecVT = IntVT; in LowerFCOPYSIGN()
7768 VecVT = MVT::v2i64; in LowerFCOPYSIGN()
7771 VecVT = MVT::v4i32; in LowerFCOPYSIGN()
7774 VecVT = MVT::v8i16; in LowerFCOPYSIGN()
15374 EVT VecVT = Vec.getValueType(); in performInsertSubvectorCombine() local
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