Lines Matching refs:VecVT
7752 EVT VecVT; in LowerFCOPYSIGN() local
7756 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In1); in LowerFCOPYSIGN()
7758 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In2); in LowerFCOPYSIGN()
7760 VecVal1 = BitCast(VecVT, In1, DAG); in LowerFCOPYSIGN()
7761 VecVal2 = BitCast(VecVT, In2, DAG); in LowerFCOPYSIGN()
7765 VecVT = IntVT; in LowerFCOPYSIGN()
7768 VecVT = MVT::v2i64; in LowerFCOPYSIGN()
7771 VecVT = MVT::v4i32; in LowerFCOPYSIGN()
7774 VecVT = MVT::v8i16; in LowerFCOPYSIGN()
7781 SDValue SignMaskV = DAG.getConstant(~APInt::getSignMask(BitWidth), DL, VecVT); in LowerFCOPYSIGN()
7787 SignMaskV = DAG.getConstant(APInt::getAllOnes(BitWidth), DL, VecVT); in LowerFCOPYSIGN()
7794 DAG.getNode(AArch64ISD::BSP, DL, VecVT, SignMaskV, VecVal1, VecVal2); in LowerFCOPYSIGN()
11345 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts); in LowerBUILD_VECTOR() local
11346 SDValue Val = DAG.getBuildVector(VecVT, dl, Ops); in LowerBUILD_VECTOR()
15374 EVT VecVT = Vec.getValueType(); in performInsertSubvectorCombine() local
15378 if (!VecVT.isFixedLengthVector() || in performInsertSubvectorCombine()
15379 !DAG.getTargetLoweringInfo().isTypeLegal(VecVT) || in performInsertSubvectorCombine()
15389 if ((SubVT.getSizeInBits() * 2) != VecVT.getSizeInBits() || in performInsertSubvectorCombine()
15406 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, Lo, Hi); in performInsertSubvectorCombine()