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Searched refs:RegVT (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCallingConvLower.cpp246 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
248 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
250 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
253 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp323 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
324 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
328 << RegVT.getEVTString() << '\n'; in LowerFormalArguments()
336 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
341 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
344 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSwitchLoweringUtils.h213 MVT RegVT; member
227 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1236 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1238 if (RegVT == MVT::i8) { in LowerFormalArguments()
1240 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1247 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1264 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1269 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1369 EVT RegVT = VA.getLocVT(); in LowerCall() local
1379 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1382 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1385 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
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/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp523 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
524 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
527 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
533 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp456 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
457 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
461 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
467 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
470 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
481 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp642 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
643 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
648 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
655 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
661 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
664 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp596 EVT RegVT = VA.getLocVT(); in LowerCall() local
607 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
610 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
613 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
616 Arg = DAG.getBitcast(RegVT, Arg); in LowerCall()
899 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
901 if (RegVT == MVT::i32) in LowerFormalArguments()
907 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
913 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
916 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp839 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
841 RegVT = VA.getValVT(); in LowerFormalArguments()
843 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
845 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
851 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
852 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
853 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
854 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
858 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
860 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1299 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
1300 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1305 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
1312 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp938 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT); in getReturnInfo() local
939 Type *PartTy = EVT(RegVT).getTypeForEVT(Context); in getReturnInfo()
H A DIRTranslator.cpp1033 B.RegVT = getMVTForLLT(MaskTy); in emitBitTestHeader()
1065 LLT SwitchTy = getLLTForMVT(BB.RegVT); in emitBitTestCase()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp2796 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
2797 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
2835 MVT VT = BB.RegVT; in visitBitTestCase()
8531 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in getRegistersForValue() local
8554 OpInfo.ConstraintVT = RegVT; in getRegistersForValue()
8575 ValueVT = RegVT; in getRegistersForValue()
8608 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); in getRegistersForValue()
8895 MVT RegVT = R->getSimpleValueType(0); in visitInlineAsm() local
8898 : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT) in visitInlineAsm()
10479 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); in LowerArguments() local
[all …]
H A DTargetLowering.cpp8301 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
8302 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
8399 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
8401 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
8405 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
8439 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
8549 MVT RegVT = getRegisterType( in expandUnalignedStore() local
8554 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
8558 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT); in expandUnalignedStore()
8577 RegVT, dl, Store, StackPtr, in expandUnalignedStore()
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H A DLegalizeIntegerTypes.cpp1568 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local
1574 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG()
1590 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp3683 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3685 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3690 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3697 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
3698 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
3699 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
3701 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
3707 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp5437 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall() local
5441 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, in prepareDescriptorIndirectCall()
5447 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff); in prepareDescriptorIndirectCall()
5449 DAG.getLoad(RegVT, dl, LDChain, AddTOC, in prepareDescriptorIndirectCall()
5454 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff); in prepareDescriptorIndirectCall()
5456 DAG.getLoad(RegVT, dl, LDChain, AddPtr, in prepareDescriptorIndirectCall()
5489 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands() local
5512 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); in buildCallOperands()
5522 RegVT)); in buildCallOperands()
6590 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in CC_AIX() local
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H A DPPCISelDAGToDAG.cpp710 EVT RegVT = ST->getValue().getValueType(); in tryTLSXFormStore() local
717 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS; in tryTLSXFormStore()
721 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS; in tryTLSXFormStore()
725 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS; in tryTLSXFormStore()
755 EVT RegVT = LD->getValueType(0); in tryTLSXFormLoad() local
761 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS; in tryTLSXFormLoad()
765 Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS; in tryTLSXFormLoad()
769 Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS; in tryTLSXFormLoad()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4066 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
4078 if (RegVT == MVT::i8) in LowerFormalArguments()
4080 else if (RegVT == MVT::i16) in LowerFormalArguments()
4082 else if (RegVT == MVT::i32) in LowerFormalArguments()
4086 else if (RegVT == MVT::f16) in LowerFormalArguments()
4088 else if (RegVT == MVT::f32) in LowerFormalArguments()
4090 else if (RegVT == MVT::f64) in LowerFormalArguments()
4092 else if (RegVT == MVT::f80) in LowerFormalArguments()
4495 EVT RegVT = VA.getLocVT(); in LowerCall() local
25744 assert(RegVT.isInteger() && in LowerLoad()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3057 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization() local
3062 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) { in IsEligibleForTailCallOptimization()
3071 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
4501 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
4529 if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
4531 else if (RegVT == MVT::f32) in LowerFormalArguments()
4533 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 || in LowerFormalArguments()
4534 RegVT == MVT::v4bf16) in LowerFormalArguments()
4536 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 || in LowerFormalArguments()
4537 RegVT == MVT::v8bf16) in LowerFormalArguments()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5836 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
5839 if (RegVT == MVT::i32) in LowerFormalArguments()
5841 else if (RegVT == MVT::i64) in LowerFormalArguments()
5843 else if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
5845 else if (RegVT == MVT::f32) in LowerFormalArguments()
5847 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
5849 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
5851 else if (RegVT.isScalableVector() && in LowerFormalArguments()
5852 RegVT.getVectorElementType() == MVT::i1) { in LowerFormalArguments()
5855 } else if (RegVT.isScalableVector()) { in LowerFormalArguments()
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