Lines Matching refs:RegVT
1236 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1238 if (RegVT == MVT::i8) { in LowerFormalArguments()
1240 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1247 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1264 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1269 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1369 EVT RegVT = VA.getLocVT(); in LowerCall() local
1379 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1382 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1385 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
1388 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); in LowerCall()