Lines Matching refs:RegVT
5437 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall() local
5441 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, in prepareDescriptorIndirectCall()
5447 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff); in prepareDescriptorIndirectCall()
5449 DAG.getLoad(RegVT, dl, LDChain, AddTOC, in prepareDescriptorIndirectCall()
5454 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff); in prepareDescriptorIndirectCall()
5456 DAG.getLoad(RegVT, dl, LDChain, AddPtr, in prepareDescriptorIndirectCall()
5489 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands() local
5512 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); in buildCallOperands()
5515 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff); in buildCallOperands()
5522 RegVT)); in buildCallOperands()
5527 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT)); in buildCallOperands()
5545 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT)); in buildCallOperands()
6590 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in CC_AIX() local
6621 State.getNextStackOffset(), RegVT, in CC_AIX()
6631 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo)); in CC_AIX()
6654 if (ValVT.getFixedSizeInBits() < RegVT.getFixedSizeInBits()) in CC_AIX()
6658 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo)); in CC_AIX()
6660 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, RegVT, LocInfo)); in CC_AIX()
6686 CCValAssign::getCustomReg(ValNo, ValVT, Reg, RegVT, LocInfo)); in CC_AIX()
6785 CCValAssign::getCustomReg(ValNo, ValVT, FirstReg, RegVT, LocInfo)); in CC_AIX()
6787 CCValAssign::getCustomReg(ValNo, ValVT, SecondReg, RegVT, LocInfo)); in CC_AIX()
6801 CCValAssign::getCustomReg(ValNo, ValVT, Reg, RegVT, LocInfo)); in CC_AIX()