4066       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()  local
4078         if (RegVT == MVT::i8)  in LowerFormalArguments()
4080         else if (RegVT == MVT::i16)  in LowerFormalArguments()
4082         else if (RegVT == MVT::i32)  in LowerFormalArguments()
4084         else if (Is64Bit && RegVT == MVT::i64)  in LowerFormalArguments()
4086         else if (RegVT == MVT::f16)  in LowerFormalArguments()
4088         else if (RegVT == MVT::f32)  in LowerFormalArguments()
4090         else if (RegVT == MVT::f64)  in LowerFormalArguments()
4092         else if (RegVT == MVT::f80)  in LowerFormalArguments()
4094         else if (RegVT == MVT::f128)  in LowerFormalArguments()
4096         else if (RegVT.is512BitVector())  in LowerFormalArguments()
4098         else if (RegVT.is256BitVector())  in LowerFormalArguments()
4100         else if (RegVT.is128BitVector())  in LowerFormalArguments()
4102         else if (RegVT == MVT::x86mmx)  in LowerFormalArguments()
4104         else if (RegVT == MVT::v1i1)  in LowerFormalArguments()
4106         else if (RegVT == MVT::v8i1)  in LowerFormalArguments()
4108         else if (RegVT == MVT::v16i1)  in LowerFormalArguments()
4110         else if (RegVT == MVT::v32i1)  in LowerFormalArguments()
4112         else if (RegVT == MVT::v64i1)  in LowerFormalArguments()
4118         ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);  in LowerFormalArguments()
4125         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,  in LowerFormalArguments()
4128         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,  in LowerFormalArguments()
4135         if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)  in LowerFormalArguments()
4142           ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);  in LowerFormalArguments()
4495     EVT RegVT = VA.getLocVT();  in LowerCall()  local
4504       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);  in LowerCall()
4507       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);  in LowerCall()
4512         Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);  in LowerCall()
4513       else if (RegVT.is128BitVector()) {  in LowerCall()
4519         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);  in LowerCall()
4522       Arg = DAG.getBitcast(RegVT, Arg);  in LowerCall()
25742   MVT RegVT = Op.getSimpleValueType();  in LowerLoad()  local
25743   assert(RegVT.isVector() && "We only custom lower vector loads.");  in LowerLoad()
25744   assert(RegVT.isInteger() &&  in LowerLoad()
25751   if (RegVT.getVectorElementType() == MVT::i1) {  in LowerLoad()
25752     assert(EVT(RegVT) == Ld->getMemoryVT() && "Expected non-extending load");  in LowerLoad()
25753     assert(RegVT.getVectorNumElements() <= 8 && "Unexpected VT");  in LowerLoad()
25765     Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT,  in LowerLoad()
48964   EVT RegVT = Ld->getValueType(0);  in combineLoad()  local
48974   if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&  in combineLoad()
48978        (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,  in combineLoad()
48981     unsigned NumElems = RegVT.getVectorNumElements();  in combineLoad()
49002     SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2);  in combineLoad()
49008   if (Ext == ISD::NON_EXTLOAD && !Subtarget.hasAVX512() && RegVT.isVector() &&  in combineLoad()
49009       RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) {  in combineLoad()
49010     unsigned NumElts = RegVT.getVectorNumElements();  in combineLoad()
49017       SDValue BoolVec = DAG.getBitcast(RegVT, IntLoad);  in combineLoad()
49025       (RegVT.is128BitVector() || RegVT.is256BitVector())) {  in combineLoad()
49036               RegVT.getFixedSizeInBits()) {  in combineLoad()
49038                                            RegVT.getSizeInBits());  in combineLoad()
49039         Extract = DAG.getBitcast(RegVT, Extract);  in combineLoad()
49053       return DAG.getLoad(RegVT, dl, Ld->getChain(), Cast, Ld->getPointerInfo(),  in combineLoad()