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Searched refs:ROTL (Results 1 – 25 of 45) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dpostlegalizercombiner-rotate.mir21 ; CHECK: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
22 ; CHECK: $w0 = COPY [[ROTL]](s32)
71 ; CHECK: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
72 ; CHECK: $w0 = COPY [[ROTL]](s32)
96 ; CHECK: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
97 ; CHECK: $w0 = COPY [[ROTL]](s32)
H A Dprelegalizercombiner-funnel-shifts-to-rotates.mir50 ; CHECK: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[COPY1]](s32)
51 ; CHECK: $w0 = COPY [[ROTL]](s32)
106 ; CHECK: [[ROTL:%[0-9]+]]:_(<4 x s32>) = G_ROTL [[COPY]], [[COPY1]](<4 x s32>)
107 ; CHECK: $q0 = COPY [[ROTL]](<4 x s32>)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Drotate.ll4 ;; select ROTL. Make sure if generates the basic ushr/shl.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Drotate.ll5 ;; select ROTL. Make sure if generates the basic VSHL/VSHR.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3547 { ISD::ROTL, MVT::v32i16, 2 }, in getIntrinsicInstrCost()
3548 { ISD::ROTL, MVT::v16i16, 2 }, in getIntrinsicInstrCost()
3549 { ISD::ROTL, MVT::v8i16, 2 }, in getIntrinsicInstrCost()
3550 { ISD::ROTL, MVT::v64i8, 5 }, in getIntrinsicInstrCost()
3551 { ISD::ROTL, MVT::v32i8, 5 }, in getIntrinsicInstrCost()
3552 { ISD::ROTL, MVT::v16i8, 5 }, in getIntrinsicInstrCost()
3561 { ISD::ROTL, MVT::v8i64, 1 }, in getIntrinsicInstrCost()
3562 { ISD::ROTL, MVT::v4i64, 1 }, in getIntrinsicInstrCost()
3563 { ISD::ROTL, MVT::v2i64, 1 }, in getIntrinsicInstrCost()
3564 { ISD::ROTL, MVT::v16i32, 1 }, in getIntrinsicInstrCost()
[all …]
H A DX86InstrShiftRotate.td862 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
867 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h694 ROTL, enumerator
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp93 setOperationAction(ISD::ROTL, MVT::i8, Custom); in AVRTargetLowering()
94 setOperationAction(ISD::ROTL, MVT::i16, Expand); in AVRTargetLowering()
291 case ISD::ROTL: { in LowerShifts()
318 case ISD::ROTL: in LowerShifts()
846 case ISD::ROTL: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td69 defm ROTL : BinaryInt<rotl, "rotl", 0x77, 0x89>;
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DLegalizerHelperTest.cpp41 auto ROTL = B.buildInstr(TargetOpcode::G_ROTL, {S32}, {Src, Amt}); in TEST_F() local
50 Helper.lower(*ROTL, 0, S32)); in TEST_F()
94 auto ROTL = B.buildInstr(TargetOpcode::G_ROTL, {S24}, {Src, Amt}); in TEST_F() local
103 Helper.lower(*ROTL, 0, S24)); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1582 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1631 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1797 setOperationAction(ISD::ROTL, MVT::i32, Legal); in HexagonTargetLowering()
1798 setOperationAction(ISD::ROTL, MVT::i64, Legal); in HexagonTargetLowering()
3216 case ISD::ROTL: return LowerROTL(Op, DAG); in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp835 case ISD::ROTL: { in expandRxSBG()
1566 case ISD::ROTL: in Select()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp81 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
83 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp339 case ISD::ROTL: in LegalizeOp()
806 case ISD::ROTL: in Expand()
H A DSelectionDAGDumper.cpp253 case ISD::ROTL: return "rotl"; in getOperationName()
H A DLegalizeIntegerTypes.cpp262 case ISD::ROTL: in PromoteIntegerResult()
1677 case ISD::ROTL: in PromoteIntegerOperand()
2548 case ISD::ROTL: in ExpandIntegerResult()
4622 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
4720 case ISD::ROTL: in ExpandIntegerOperand()
H A DDAGCombiner.cpp1723 case ISD::ROTL: return visitRotate(N); in visit()
6844 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) in MatchBSwapHWord()
6845 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt); in MatchBSwapHWord()
7502 bool HasROTL = hasOperation(ISD::ROTL, VT); in MatchRotate()
7641 SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt); in MatchRotate()
7646 SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt); in MatchRotate()
7707 RExtOp0, HasROTL, ISD::ROTL, ISD::ROTR, DL); in MatchRotate()
7713 LExtOp0, HasROTR, ISD::ROTR, ISD::ROTL, DL); in MatchRotate()
8836 if (NextOp == ISD::ROTL || NextOp == ISD::ROTR) { in visitRotate()
9801 unsigned RotOpc = IsFSHL ? ISD::ROTL : ISD::ROTR; in visitFunnelShift()
[all …]
H A DTargetLowering.cpp2030 case ISD::ROTL: in SimplifyDemandedBits()
2034 bool IsROTL = (Op.getOpcode() == ISD::ROTL); in SimplifyDemandedBits()
3345 case ISD::ROTL: in SimplifyDemandedVectorElts()
4033 if (X.getOpcode() == ISD::ROTL || X.getOpcode() == ISD::ROTR) in foldSetCCWithRotate()
7223 bool IsLeft = Node->getOpcode() == ISD::ROTL; in expandROT()
7232 unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL; in expandROT()
8092 return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp111 setOperationAction(ISD::ROTL, VT, Expand); in BPFTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp442 setOperationAction(ISD::ROTL, MVT::i64, Legal); in NVPTXTargetLowering()
444 setOperationAction(ISD::ROTL, MVT::i32, Legal); in NVPTXTargetLowering()
447 setOperationAction(ISD::ROTL, MVT::i16, Expand); in NVPTXTargetLowering()
449 setOperationAction(ISD::ROTL, MVT::i8, Expand); in NVPTXTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp248 setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom); in RISCVTargetLowering()
250 setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand); in RISCVTargetLowering()
557 setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand); in RISCVTargetLowering()
950 setTargetDAGCombine({ISD::ROTL, ISD::ROTR}); in RISCVTargetLowering()
6799 case ISD::ROTL: in getRISCVWOpcode()
6982 case ISD::ROTL: in ReplaceNodeResults()
7670 if ((Reverse.getOpcode() == ISD::ROTL || in combineORToGORC()
7866 assert((N->getOpcode() == ISD::ROTR || N->getOpcode() == ISD::ROTL || in combineROTR_ROTL_RORW_ROLW()
8159 TLI.isOperationLegal(ISD::ROTL, MVT::i64)) { in performXORCombine()
8899 case ISD::ROTL: in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp120 setOperationAction(ISD::ROTL, MVT::i32, Expand); in LanaiTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp683 } else if (Opcode == ISD::ROTL) { in isRotateAndMask()
1470 case ISD::ROTL: in getValueBits()
3931 case ISD::ROTL: in tryBitPermutation()
4742 if (isRunOfOnes(Imm, MB, ME) && Val.getOpcode() != ISD::ROTL) { in tryAsSingleRLWINM()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1677 setOperationAction(ISD::ROTL , MVT::i64, Expand); in SparcTargetLowering()
1743 setOperationAction(ISD::ROTL , MVT::i32, Expand); in SparcTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp107 setOperationAction(ISD::ROTL , MVT::i32, Expand); in XCoreTargetLowering()

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