| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RegisterPressure.cpp | 54 if (PrevMask.any() || NewMask.none()) in increaseSetPressure() 68 if (NewMask.any() || PrevMask.none()) in decreaseSetPressure() 158 if (PreviousMask.any() || NewMask.none()) in increaseRegPressure() 710 LaneBitmask NewMask = PrevMask | P.LaneMask; in addLiveRegs() local 724 LaneBitmask NewMask; in discoverLiveInOrOut() local 727 NewMask = Pair.LaneMask; in discoverLiveInOrOut() 731 NewMask = PrevMask | Pair.LaneMask; in discoverLiveInOrOut() 732 I->LaneMask = NewMask; in discoverLiveInOrOut() 789 if (NewMask.none()) { in recede() 809 if (NewMask == PreviousMask) in recede() [all …]
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| /llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/ |
| H A D | ReduceRegisterMasks.cpp | 41 std::vector<uint32_t> NewMask(RegMaskSize); in reduceMasksInFunction() local 47 NewMask[I / 32] |= 1u << (I % 32); in reduceMasksInFunction() 54 std::memcpy(UpdatedMask, NewMask.data(), in reduceMasksInFunction()
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | VectorBuilder.h | 73 VectorBuilder &setMask(Value *NewMask) { in setMask() argument 74 Mask = NewMask; in setMask()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kCollapseMOVEMPass.cpp | 93 UpdateType classifyUpdateByMask(unsigned NewMask) const { in classifyUpdateByMask() 94 assert(NewMask && "Mask needs to select at least one register"); in classifyUpdateByMask() 96 if (NewMask > Mask) { in classifyUpdateByMask() 98 } else if (NewMask < Mask) { in classifyUpdateByMask()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 86 LaneBitmask NewMask, in inc() argument 88 if (SIRegisterInfo::getNumCoveredRegs(NewMask) == in inc() 93 if (NewMask < PrevMask) { in inc() 94 std::swap(NewMask, PrevMask); in inc() 108 assert(PrevMask < NewMask); in inc() 111 Sign * SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask); in inc() 114 assert(NewMask.any()); in inc()
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| H A D | SIModeRegister.cpp | 37 Status(unsigned NewMask, unsigned NewMode) : Mask(NewMask), Mode(NewMode) { in Status() 56 unsigned NewMask = (Mask & S.Mask) & (Mode ^ ~S.Mode); in intersect() local 57 unsigned NewMode = (Mode & NewMask); in intersect() 58 return Status(NewMask, NewMode); in intersect()
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| H A D | GCNRegPressure.h | 70 LaneBitmask NewMask,
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| H A D | AMDGPUInstructionSelector.cpp | 2846 static Register normalizeVOP3PMask(int NewMask[2], Register Src0, Register Src1, in normalizeVOP3PMask() 2848 NewMask[0] = Mask[0]; in normalizeVOP3PMask() 2849 NewMask[1] = Mask[1]; in normalizeVOP3PMask() 2853 assert(NewMask[0] == 2 || NewMask[0] == 3 || NewMask[0] == -1); in normalizeVOP3PMask() 2854 assert(NewMask[1] == 2 || NewMask[1] == 3 || NewMask[1] == -1); in normalizeVOP3PMask() 2857 NewMask[0] = NewMask[0] == -1 ? -1 : NewMask[0] - 2; in normalizeVOP3PMask() 2858 NewMask[1] = NewMask[1] == -1 ? -1 : NewMask[1] - 2; in normalizeVOP3PMask()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 512 SDValue NewMask; in getTargetSplitMask() local 514 NewMask = getConstantMask(Packing::Normal, true); in getTargetSplitMask() 516 NewMask = getUnpack(MVT::v256i1, RawMask, Part, NewAVL); in getTargetSplitMask() 518 return VETargetMasks(NewMask, NewAVL); in getTargetSplitMask()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 1272 SmallVector<int, 16> NewMask(NumMaskElts); in foldInsEltIntoSplat() local 1276 return new ShuffleVectorInst(Op0, NewMask); in foldInsEltIntoSplat() 1311 SmallVector<int, 16> NewMask(NumMaskElts); in foldInsEltIntoIdentityShuffle() local 1316 NewMask[i] = OldMask[i]; in foldInsEltIntoIdentityShuffle() 1324 NewMask[i] = IdxC; in foldInsEltIntoIdentityShuffle() 2040 SmallVector<int, 16> NewMask(NumMaskElts, 0); in canonicalizeInsertSplat() local 2043 NewMask[i] = Mask[i]; in canonicalizeInsertSplat() 2376 SmallVector<int, 16> NewMask(NumElts); in foldIdentityExtractShuffle() local 2385 return new ShuffleVectorInst(X, Y, NewMask); in foldIdentityExtractShuffle() 2535 NewMask[i] = Mask[i]; in foldIdentityPaddedShuffles() [all …]
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| H A D | InstCombineShifts.cpp | 222 Constant *NewMask; in dropRedundantMaskingOfLeftShiftInput() local 253 NewMask = ConstantExpr::getNot(ExtendedInvertedMask); in dropRedundantMaskingOfLeftShiftInput() 289 NewMask = in dropRedundantMaskingOfLeftShiftInput() 294 NewMask = ConstantExpr::getTrunc(NewMask, NarrowestTy); in dropRedundantMaskingOfLeftShiftInput() 297 bool NeedMask = !match(NewMask, m_AllOnes()); in dropRedundantMaskingOfLeftShiftInput() 322 return BinaryOperator::Create(Instruction::And, NewShift, NewMask); in dropRedundantMaskingOfLeftShiftInput()
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| H A D | InstCombineAndOrXor.cpp | 207 unsigned NewMask; in conjugateICmpMask() local 208 NewMask = (Mask & (AMask_AllOnes | BMask_AllOnes | Mask_AllZeros | in conjugateICmpMask() 216 return NewMask; in conjugateICmpMask() 430 Value *NewMask = ConstantInt::get(A->getType(), BorD); in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed() local 432 Value *NewAnd = Builder.CreateAnd(A, NewMask); in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed() 612 APInt NewMask = *ConstB & *ConstD; in foldLogOpOfMaskedICmps() local 613 if (NewMask == *ConstB) in foldLogOpOfMaskedICmps() 615 else if (NewMask == *ConstD) in foldLogOpOfMaskedICmps() 624 APInt NewMask = *ConstB | *ConstD; in foldLogOpOfMaskedICmps() local 625 if (NewMask == *ConstB) in foldLogOpOfMaskedICmps() [all …]
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| H A D | InstCombineSimplifyDemanded.cpp | 321 APInt NewMask = ~(LHSKnown.One & RHSKnown.One & DemandedMask); in SimplifyDemandedUseBits() local 323 Constant *AndC = ConstantInt::get(VTy, NewMask & AndRHS->getValue()); in SimplifyDemandedUseBits() 327 Constant *XorC = ConstantInt::get(VTy, NewMask & XorRHS->getValue()); in SimplifyDemandedUseBits()
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| H A D | InstCombineAddSub.cpp | 1375 Constant *NewMask = ConstantInt::get(RHS->getType(), *C1 - 1); in visitAdd() local 1376 return BinaryOperator::CreateAnd(A, NewMask); in visitAdd()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | RegisterPressure.h | 551 LaneBitmask NewMask); 553 LaneBitmask NewMask);
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 853 MutableArrayRef<int> NewMask, unsigned Options = None); 855 MutableArrayRef<int> NewMask); 1118 ResultStack &Results, MutableArrayRef<int> NewMask, in packs() argument 1197 NewMask[I] = M; in packs() 1302 NewMask[I] = M; in packs() 1330 NewMask[I] = M; in packs() 1342 ResultStack &Results, MutableArrayRef<int> NewMask) { in packp() argument 1374 packSegmentMask(SM.Mask, SegList, HwLen, NewMask); in packp()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 688 NewMask[I] = Mask[SubMask[I]]; in addMask() 690 Mask.swap(NewMask); in addMask() 5784 Mask.swap(NewMask); in buildShuffleEntryMask() 6078 SmallVector<int> NewMask; in getEntryCost() local 6086 ::addMask(Mask, NewMask); in getEntryCost() 7656 SmallVector<int, 4> NewMask; in addInversedMask() local 7658 addMask(NewMask); in addInversedMask() 7664 addMask(NewMask); in addMask() 8658 Mask.swap(NewMask); in vectorizeTree() 8979 NewMask[I] != SM1[I]) in optimizeGatherSequence() [all …]
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| H A D | VectorCombine.cpp | 558 SmallVector<int, 16> NewMask; in foldBitcastShuf() local 564 narrowShuffleMaskElts(ScaleFactor, Mask, NewMask); in foldBitcastShuf() 570 if (!widenShuffleMaskElts(ScaleFactor, Mask, NewMask)) in foldBitcastShuf() 577 TargetTransformInfo::SK_PermuteSingleSrc, DestTy, NewMask); in foldBitcastShuf() 586 Value *Shuf = Builder.CreateShuffleVector(CastV, NewMask); in foldBitcastShuf()
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| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | IntrinsicInst.cpp | 354 void VPIntrinsic::setMaskParam(Value *NewMask) { in setMaskParam() argument 356 setArgOperand(*MaskPos, NewMask); in setMaskParam()
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| H A D | Instructions.cpp | 2041 SmallVector<int, 16> NewMask(NumMaskElts); in commute() local 2045 NewMask[i] = UndefMaskElem; in commute() 2050 NewMask[i] = MaskElt; in commute() 2052 setShuffleMask(NewMask); in commute()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1922 SDValue NewMask = DAG.getConstant(0xff, DL, VT); in foldMaskAndShiftToExtract() local 1924 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); in foldMaskAndShiftToExtract() 1935 insertDAGNode(DAG, N, NewMask); in foldMaskAndShiftToExtract() 1994 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT); in foldMaskedShiftToScaledMask() local 1995 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask); in foldMaskedShiftToScaledMask() 2003 insertDAGNode(DAG, N, NewMask); in foldMaskedShiftToScaledMask() 2160 SDValue NewMask = DAG.getConstant(Mask >> AMShiftAmt, DL, VT); in foldMaskedShiftToBEXTR() local 2161 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, NewSRL, NewMask); in foldMaskedShiftToBEXTR() 2172 insertDAGNode(DAG, N, NewMask); in foldMaskedShiftToBEXTR() 4466 SDValue NewMask = CurDAG->getConstant(NegMaskVal, SDLoc(And), VT); in shrinkAndImmediate() local [all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 13844 SmallVector<int, 8> NewMask; in visitBITCAST() local 19430 assert(NewMask[InsIndex] < in combineInsertEltToShuffle() 21570 SmallVector<int, 16> NewMask; in foldExtractSubvectorFromShuffleVector() local 21583 NewMask.emplace_back(M); in foldExtractSubvectorFromShuffleVector() 21611 NewMask.emplace_back(-1); in foldExtractSubvectorFromShuffleVector() 21638 NewMask.emplace_back(AdjM); in foldExtractSubvectorFromShuffleVector() 22249 SmallVector<int, 32> NewMask; in combineShuffleOfSplatVal() local 22289 SmallVector<int> NewMask; in combineShuffleOfBitcast() local 22495 NewMask.push_back(Idx); in visitVECTOR_SHUFFLE() 22633 NewMask.push_back(Idx); in visitVECTOR_SHUFFLE() [all …]
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| H A D | LegalizeDAG.cpp | 268 SmallVector<int, 8> NewMask; in ShuffleWithNarrowerEltType() local 273 NewMask.push_back(-1); in ShuffleWithNarrowerEltType() 275 NewMask.push_back(Idx * NumEltsGrowth + j); in ShuffleWithNarrowerEltType() 278 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); in ShuffleWithNarrowerEltType() 279 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); in ShuffleWithNarrowerEltType() 280 return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask); in ShuffleWithNarrowerEltType() 3036 SmallVector<int, 32> NewMask; in ExpandNode() local 3074 NewMask.push_back(Mask[i]); in ExpandNode() 3078 NewMask.push_back(Mask[i]*factor+fi); in ExpandNode() 3081 Mask = NewMask; in ExpandNode()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 9467 if (NewMask == Mask) in targetShrinkDemandedConstant() 9486 if (IsLegalMask(NewMask)) in targetShrinkDemandedConstant() 9487 return UseMask(NewMask); in targetShrinkDemandedConstant() 9492 APInt NewMask = APInt(64, 0xffffffff); in targetShrinkDemandedConstant() local 9493 if (IsLegalMask(NewMask)) in targetShrinkDemandedConstant() 9494 return UseMask(NewMask); in targetShrinkDemandedConstant() 9509 APInt NewMask = ShrunkMask; in targetShrinkDemandedConstant() local 9511 NewMask.setBitsFrom(11); in targetShrinkDemandedConstant() 9513 NewMask.setBitsFrom(31); in targetShrinkDemandedConstant() 9518 assert(IsLegalMask(NewMask)); in targetShrinkDemandedConstant() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 341 unsigned NewMask = 0; in rewindImplicitITPosition() local 342 NewMask |= ITState.Mask & (0xC << TZ); in rewindImplicitITPosition() 343 NewMask |= 0x2 << TZ; in rewindImplicitITPosition() 344 ITState.Mask = NewMask; in rewindImplicitITPosition() 389 unsigned NewMask = 0; in extendImplicitITBlock() local 391 NewMask |= ITState.Mask & (0xE << TZ); in extendImplicitITBlock() 393 NewMask |= (Cond != ITState.Cond) << TZ; in extendImplicitITBlock() 395 NewMask |= 1 << (TZ - 1); in extendImplicitITBlock() 396 ITState.Mask = NewMask; in extendImplicitITBlock()
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