[llvm] Use value instead of getValue (NFC)

[llvm] Don't use Optional::hasValue (NFC)

This patch replaces Optional::hasValue with the implicit cast to bool
in conditionals only.

Revert "Don't use Optional::hasValue (NFC)"

This reverts commit aa8feeefd3ac6c78ee8f67bf033976fc7d68bc6d.

Don't use Optional::hasValue (NFC)

[InstCombine] [InstCombine] reduce left-shift-of-right-shifted constant via demanded bits

If we don't demand low bits and it is valid to pre-shift a constant:
(C2 >> X) << C1 --> (C2 << C1) >> X

ht

[InstCombine] [InstCombine] reduce left-shift-of-right-shifted constant via demanded bits

If we don't demand low bits and it is valid to pre-shift a constant:
(C2 >> X) << C1 --> (C2 << C1) >> X

https://alive2.llvm.org/ce/z/_UzTMP

This is the reverse-order shift sibling to 82040d414b3c ( D127122 ).
It seems likely that we would want to add this to the SDAG version of
the code too to keep it on par with IR.

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[InstCombine] reduce code duplication for accessing type; NFC

[InstCombine] reduce right-shift-of-left-shifted constant via demanded bits

If we don't demand high bits (zeros) and it is valid to pre-shift a constant:
(C2 << X) >> C1 --> (C2 >> C1) << X

https:/

[InstCombine] reduce right-shift-of-left-shifted constant via demanded bits

If we don't demand high bits (zeros) and it is valid to pre-shift a constant:
(C2 << X) >> C1 --> (C2 >> C1) << X

https://alive2.llvm.org/ce/z/P3dWDW

There are a variety of related patterns, but I haven't found a single solution
that gets all of the motivating examples - so pulling this piece out of
D126617 along with more tests.

We should also handle the case where we shift-right followed by shift-left,
but I'll make that a follow-on patch assuming this one is ok. It seems likely
that we would want to add this to the SDAG version of the code too to keep it
on par with IR.

Differential Revision: https://reviews.llvm.org/D127122

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[InstCombine] SimplifyDemandedUseBits - allow and(srem(X,Pow2),C) -> and(X,C) to work on vector types

Replace m_ConstantInt with m_APInt to match uniform (no-undef) vector remainder amounts.

[InstCombine] SimplifyDemandedUseBits - add TODO to remove shl node if we only demand known sign bits of the shift source

Similar to what we already perform for ashr/lshr

[InstCombine] SimplifyDemandedUseBits - remove lshr node if we only demand known sign bit

This is a lshr equivalent to D122340 - if we don't demand any of the additional sign bits introduced by the

[InstCombine] SimplifyDemandedUseBits - remove lshr node if we only demand known sign bit

This is a lshr equivalent to D122340 - if we don't demand any of the additional sign bits introduced by the ashr, the lshr can be treated as an ashr and we can remove the shift entirely if we only demand already known sign bits.

Another step towards PR21929

https://alive2.llvm.org/ce/z/6f3kjq

Differential Revision: https://reviews.llvm.org/D123118

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[InstCombine] SimplifyDemandedUseBits - remove ashr node if we only demand known sign bits

We already do this for SelectionDAG, but we're missing it here.

Noticed while re-triaging PR21929

Differe

[InstCombine] SimplifyDemandedUseBits - remove ashr node if we only demand known sign bits

We already do this for SelectionDAG, but we're missing it here.

Noticed while re-triaging PR21929

Differential Revision: https://reviews.llvm.org/D122340

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Cleanup includes: Transform/Scalar

Estimated impact on preprocessor output line:
before: 1062981579
after: 1062494547

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cl

Cleanup includes: Transform/Scalar

Estimated impact on preprocessor output line:
before: 1062981579
after: 1062494547

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D120817

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Cleanup includes: TransformsUtils

Estimation on the impact on preprocessor output:
before: 1065307662
after: 1064800684

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-

Cleanup includes: TransformsUtils

Estimation on the impact on preprocessor output:
before: 1065307662
after: 1064800684

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D120741

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[InstCombine] Remove SPF min/max check from select demanded bits (NFCI)

This should no longer be necessary now that we canonicalize to
intrinsics. This may not be entirely NFC in practice if worklis

[InstCombine] Remove SPF min/max check from select demanded bits (NFCI)

This should no longer be necessary now that we canonicalize to
intrinsics. This may not be entirely NFC in practice if worklist
order gets inverted and we perform demanded bits simplification
of a select user before the select is canonicalized.

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[InstCombine] reduce mul operands based on undemanded high bits

We already do this in SDAG, but mul was left out of the fold
for unused high bits in IR.

The high bits of a mul's operands do not cha

[InstCombine] reduce mul operands based on undemanded high bits

We already do this in SDAG, but mul was left out of the fold
for unused high bits in IR.

The high bits of a mul's operands do not change the low bits
of the result:
https://alive2.llvm.org/ce/z/XRj5Ek

Verify some test diffs to confirm that they are correct:
https://alive2.llvm.org/ce/z/y_W8DW
https://alive2.llvm.org/ce/z/7DM5uf
https://alive2.llvm.org/ce/z/GDiHCK

This gets a fold that was presumed not possible in D114272:
https://alive2.llvm.org/ce/z/tAN-WY

Removing nsw/nuw is needed for general correctness (and is
also done in the codegen version), but we might be able to
recover more of those with better analysis.

Differential Revision: https://reviews.llvm.org/D119369

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[InstCombine] generalize 2 LSB of demanded bits for X*X

This is a follow-up suggested in D119060.
Instead of checking each of the bottom 2 bits individually,
we can check them together and handle th

[InstCombine] generalize 2 LSB of demanded bits for X*X

This is a follow-up suggested in D119060.
Instead of checking each of the bottom 2 bits individually,
we can check them together and handle the possibility that
we demand both together.

https://alive2.llvm.org/ce/z/C2ihC2

Differential Revision: https://reviews.llvm.org/D119139

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[InstCombine] SimplifyDemandedBits - mul(x,x) is odd iff x is odd

https://alive2.llvm.org/ce/z/AXPr3k

[InstCombine] SimplifyDemandedBits - mul(x,x) - if only demand bit[1] then fold to zero

This is a translation of the fold added to codegen with:
2d1390efbe61

Part of solving issue #48027

[InstCombine] try to fold one-demanded-bit-of-multiply

This is a generalization of the icmp fold in D118061 (and that can be abandoned).
We're looking for a disguised form of "odd * odd must be odd"

[InstCombine] try to fold one-demanded-bit-of-multiply

This is a generalization of the icmp fold in D118061 (and that can be abandoned).
We're looking for a disguised form of "odd * odd must be odd".
Some Alive2 proofs to show correctness:
https://alive2.llvm.org/ce/z/60Y8hz
https://alive2.llvm.org/ce/z/HfAP6R

Differential Revision: https://reviews.llvm.org/D118539

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[InstCombine] remove incorrect gep(x, undef) -> undef optimization
gep(x, undef) carries the provenance of x, so we can't replace it with any
pointer like undef.
This leaves room for improvement for

[InstCombine] remove incorrect gep(x, undef) -> undef optimization
gep(x, undef) carries the provenance of x, so we can't replace it with any
pointer like undef.
This leaves room for improvement for the poison case, but that's currently
not possible as the demanded bits API doesn't distinguish between undef &
poison bits.

Fixes #44790

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[TargetLowering][InstCombine] Simplify BSwap demanded bits code a little. NFC

Use alignDown instead of &= ~7.

Replace ResultBit with NLZ. (BitWidth - NLZ - NTZ == 8) so
(BitWidth - NTZ - 8 == NLZ).

[TargetLowering][InstCombine] Simplify BSwap demanded bits code a little. NFC

Use alignDown instead of &= ~7.

Replace ResultBit with NLZ. (BitWidth - NLZ - NTZ == 8) so
(BitWidth - NTZ - 8 == NLZ).

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D117804

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[InstCombine] don't automatically drop poison-generating flags in SimplifyVectorDemandedElts

I noticed this while reviewing the test diffs in D115460
(and so the diffs in that patch will be reduced

[InstCombine] don't automatically drop poison-generating flags in SimplifyVectorDemandedElts

I noticed this while reviewing the test diffs in D115460
(and so the diffs in that patch will be reduced if this one is applied first).

This is effectively a revert of 3436dc29239d ( https://reviews.llvm.org/rG3436dc29239d ) -
since that commit, we've made several enhancements, so the reasoning there is no longer
valid. Specifically, we added a poison value to IR, and we clarified the behavior of
undef/poison elements in a shuffle mask:
https://llvm.org/docs/LangRef.html#shufflevector-instruction

Alive2 seems to agree that the propagation of flags in the test diffs shown here are valid:
https://alive2.llvm.org/ce/z/UuY-jr
https://alive2.llvm.org/ce/z/GXoMD9
https://alive2.llvm.org/ce/z/nVCyVH

Differential Revision: https://reviews.llvm.org/D115526

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[APInt] Stop using soft-deprecated constructors and methods in llvm. NFC.

Stop using APInt constructors and methods that were soft-deprecated in
D109483. This fixes all the uses I found in llvm, exc

[APInt] Stop using soft-deprecated constructors and methods in llvm. NFC.

Stop using APInt constructors and methods that were soft-deprecated in
D109483. This fixes all the uses I found in llvm, except for the APInt
unit tests which should still test the deprecated methods.

Differential Revision: https://reviews.llvm.org/D110807

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[InstCombine] fold cast of right-shift if high bits are not demanded (3rd try)

The first two tries at this were reverted because they caused an
infinite loop in instcombine.
That should be fixed aft

[InstCombine] fold cast of right-shift if high bits are not demanded (3rd try)

The first two tries at this were reverted because they caused an
infinite loop in instcombine.
That should be fixed after a series of patches that ended with
removing the faulty opposing transform:
3fabd98e5b3e

Original commit message:
(masked) trunc (lshr X, C) --> (masked) lshr (trunc X), C

Narrowing the shift should be better for analysis and can lead
to follow-on transforms as shown.

Attempt at a general proof in Alive2:
https://alive2.llvm.org/ce/z/tRnnSF

Here are a couple of the specific tests:
https://alive2.llvm.org/ce/z/bCnTp-
https://alive2.llvm.org/ce/z/TfaHnb

Differential Revision: https://reviews.llvm.org/D110170

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Revert "[InstCombine] fold cast of right-shift if high bits are not demanded (2nd try)"

This reverts commit bb9333c3504a4a02b982526ad8264d14c6ec1ad4.

This exposes another existing bug that causes a

Revert "[InstCombine] fold cast of right-shift if high bits are not demanded (2nd try)"

This reverts commit bb9333c3504a4a02b982526ad8264d14c6ec1ad4.

This exposes another existing bug that causes an infinite loop as shown in
D110170
...so reverting while I look at another fix.

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