| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | neon-idiv.ll | 7 ; to MULHS due the simplification by multiplying by a magic number
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 210 case ISD::MULHS: in trySelect()
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| H A D | MipsSEISelLowering.cpp | 178 setOperationAction(ISD::MULHS, MVT::i32, Custom); in MipsSETargetLowering()
189 setOperationAction(ISD::MULHS, MVT::i64, Custom); in MipsSETargetLowering()
226 setOperationAction(ISD::MULHS, MVT::i32, Legal); in MipsSETargetLowering()
273 setOperationAction(ISD::MULHS, MVT::i64, Legal); in MipsSETargetLowering()
449 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 638 MULHS, enumerator
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| H A D | TargetLowering.h | 2611 case ISD::MULHS: in isCommutativeBinOp()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 193 setOperationAction(ISD::MULHS, T, Custom); in initializeHVXLowering()
267 setOperationAction(ISD::MULHS, T, Custom); in initializeHVXLowering()
1709 bool IsSigned = Op.getOpcode() == ISD::MULHS; in LowerHvxMulh()
2419 case ISD::MULHS: in LowerHvxOperation()
2460 case ISD::MULHS: in LowerHvxOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 388 X86_INTRINSIC_DATA(avx2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
839 X86_INTRINSIC_DATA(avx512_pmulh_w_512, INTR_TYPE_2OP, ISD::MULHS, 0),
1289 X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
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| H A D | X86ISelLowering.cpp | 336 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
927 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
1455 setOperationAction(ISD::MULHS, MVT::v8i32, Custom); in X86TargetLowering()
1459 setOperationAction(ISD::MULHS, MVT::v32i8, Custom); in X86TargetLowering()
1782 setOperationAction(ISD::MULHS, MVT::v16i32, Custom); in X86TargetLowering()
1785 setOperationAction(ISD::MULHS, MVT::v64i8, Custom); in X86TargetLowering()
29222 unsigned MulOpc = IsSigned ? ISD::MULHS : ISD::MUL; in LowervXi8MulWithUNPCK()
29236 bool IsSigned = Op->getOpcode() == ISD::MULHS; in LowerMULH()
30058 SDValue Res = DAG.getNode(ISD::MULHS, dl, VT, R, Scale); in LowerShift()
32317 case ISD::MULHS: in LowerOperation()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 122 setOperationAction(ISD::MULHS, MVT::i8, Promote); in MSP430TargetLowering()
127 setOperationAction(ISD::MULHS, MVT::i16, Expand); in MSP430TargetLowering()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 232 case ISD::MULHS: return "mulhs"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 318 case ISD::MULHS: in LegalizeOp()
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| H A D | TargetLowering.cpp | 5879 if (isOperationLegalOrCustom(ISD::MULHS, VT, IsAfterLegalization)) in BuildSDIV()
5880 return DAG.getNode(ISD::MULHS, dl, VT, X, Y); in BuildSDIV()
6943 isOperationLegalOrCustom(ISD::MULHS, HiLoVT); in expandMUL_LOHI()
6971 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R); in expandMUL_LOHI()
9044 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU; in expandFixedPointMul()
9328 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; in expandMULO()
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| H A D | LegalizeDAG.cpp | 3315 case ISD::MULHS: { in ExpandNode()
3332 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; in ExpandNode()
3369 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); in ExpandNode()
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 107 setOperationAction(ISD::MULHS, VT, Expand); in BPFTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 140 setOperationAction(ISD::MULHS, MVT::i32, Legal); in ARCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 356 setOperationAction({ISD::MULHU, ISD::MULHS}, MVT::i16, Expand); in AMDGPUTargetLowering()
358 setOperationAction({ISD::MUL, ISD::MULHU, ISD::MULHS}, MVT::i64, Expand); in AMDGPUTargetLowering()
378 ISD::MULHS, ISD::OR, ISD::SHL, in AMDGPUTargetLowering()
472 ISD::MULHU, ISD::MULHS, in AMDGPUTargetLowering()
4033 case ISD::MULHS: in PerformDAGCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 76 setOperationAction(ISD::MULHS, MVT::i32, Expand); in CSKYTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 115 setOperationAction(ISD::MULHS, MVT::i32, Expand); in LanaiTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1759 setOperationAction(ISD::MULHS, MVT::i32, Expand); in SparcTargetLowering()
1782 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 179 setOperationAction(ISD::MULHS, VT, Expand); in AVRTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 99 setOperationAction(ISD::MULHS, MVT::i32, Expand); in XCoreTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 525 setOperationAction(ISD::MULHS, MVT::i32, Expand); in AArch64TargetLowering()
1082 setOperationAction(ISD::MULHS, VT, Legal); in AArch64TargetLowering()
1085 setOperationAction(ISD::MULHS, VT, Expand); in AArch64TargetLowering()
1162 setOperationAction(ISD::MULHS, VT, Custom); in AArch64TargetLowering()
1398 setOperationAction(ISD::MULHS, MVT::v1i64, Custom); in AArch64TargetLowering()
1399 setOperationAction(ISD::MULHS, MVT::v2i64, Custom); in AArch64TargetLowering()
1673 setOperationAction(ISD::MULHS, VT, Custom); in addTypeForFixedLengthSVE()
3450 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
5516 case ISD::MULHS: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 143 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU, in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 177 setOperationAction(ISD::MULHS, IntVT, Expand); in initSPUActions()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
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