336     setOperationAction(ISD::MULHS, VT, Expand);  in X86TargetLowering()
927     setOperationAction(ISD::MULHS, VT, Expand);  in X86TargetLowering()
1033     setOperationAction(ISD::MULHS,              MVT::v4i32, Custom);  in X86TargetLowering()
1035     setOperationAction(ISD::MULHS,              MVT::v16i8, Custom);  in X86TargetLowering()
1037     setOperationAction(ISD::MULHS,              MVT::v8i16, Legal);  in X86TargetLowering()
1455     setOperationAction(ISD::MULHS,     MVT::v8i32,  Custom);  in X86TargetLowering()
1457     setOperationAction(ISD::MULHS,     MVT::v16i16, HasInt256 ? Legal : Custom);  in X86TargetLowering()
1459     setOperationAction(ISD::MULHS,     MVT::v32i8,  Custom);  in X86TargetLowering()
1782     setOperationAction(ISD::MULHS, MVT::v16i32, Custom);  in X86TargetLowering()
1783     setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom);  in X86TargetLowering()
1785     setOperationAction(ISD::MULHS, MVT::v64i8,  Custom);  in X86TargetLowering()
29222   unsigned MulOpc = IsSigned ? ISD::MULHS : ISD::MUL;  in LowervXi8MulWithUNPCK()
29236   bool IsSigned = Op->getOpcode() == ISD::MULHS;  in LowerMULH()
30058       SDValue Res = DAG.getNode(ISD::MULHS, dl, VT, R, Scale);  in LowerShift()
32317   case ISD::MULHS:  in LowerOperation()
46093       DAG.getNode(Mode == ShrinkMode::MULS16 ? ISD::MULHS : ISD::MULHU, DL,  in reduceVMULWidth()
46555   unsigned Opc = ExtOpc == ISD::SIGN_EXTEND ? ISD::MULHS : ISD::MULHU;  in combineShiftToPMULH()
47943     if ((Opc0 == ISD::MUL || Opc0 == ISD::MULHU || Opc0 == ISD::MULHS) &&  in combineAnd()
50393   unsigned Opc = IsSigned ? ISD::MULHS : ISD::MULHU;  in combinePMULH()