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Searched refs:EltSize (Results 1 – 25 of 60) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.cpp399 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, in DecodeEXTRQIMask() argument
409 if (0 != (Len % EltSize) || 0 != (Idx % EltSize)) in DecodeEXTRQIMask()
423 Len /= EltSize; in DecodeEXTRQIMask()
424 Idx /= EltSize; in DecodeEXTRQIMask()
436 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, in DecodeINSERTQIMask() argument
446 if (0 != (Len % EltSize) || 0 != (Idx % EltSize)) in DecodeINSERTQIMask()
460 Len /= EltSize; in DecodeINSERTQIMask()
461 Idx /= EltSize; in DecodeINSERTQIMask()
H A DX86ShuffleDecode.h140 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
144 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp108 unsigned EltSize; member
220 unsigned read2Opcode(unsigned EltSize) const;
226 unsigned write2Opcode(unsigned EltSize) const;
654 EltSize = in setMI()
659 EltSize = in setMI()
667 EltSize = 4; in setMI()
878 if ((CI.Offset % CI.EltSize != 0) || (Paired.Offset % CI.EltSize != 0)) in offsetsCanBeCombined()
952 CI.BaseOff = BaseOff * CI.EltSize; in offsetsCanBeCombined()
966 CI.BaseOff = BaseOff * CI.EltSize; in offsetsCanBeCombined()
1099 CI.UseST64 ? read2ST64Opcode(CI.EltSize) : read2Opcode(CI.EltSize); in mergeRead2Pair()
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H A DR600TargetTransformInfo.cpp115 unsigned EltSize = in getVectorInstrCost() local
117 if (EltSize < 32) { in getVectorInstrCost()
H A DSIRegisterInfo.cpp99 unsigned EltSize = 4; member
1241 switch (EltSize) { in getFlatScratchSpillOpcode()
1299 unsigned Size = NumSubRegs * EltSize; in buildSpillLoadStore()
1308 if (IsFlat && EltSize > 4) { in buildSpillLoadStore()
1459 ++i, RegOffset += EltSize) { in buildSpillLoadStore()
1461 EltSize = RemSize; in buildSpillLoadStore()
1482 unsigned NumRegs = EltSize / 4; in buildSpillLoadStore()
1504 unsigned RemEltSize = EltSize; in buildSpillLoadStore()
1540 assert(IsFlat && EltSize > 4); in buildSpillLoadStore()
1552 assert(EltSize == 4); in buildSpillLoadStore()
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H A DAMDGPULegalizerInfo.cpp75 EltSize > 1 && EltSize < 32 && in isSmallOddVector()
128 assert(EltSize < 32); in moreEltsToNext32Bit()
130 const int NewNumElts = (32 * NextMul32 + EltSize - 1) / EltSize; in moreEltsToNext32Bit()
190 const int EltSize = EltTy.getSizeInBits(); in isRegisterVectorElementType() local
191 return EltSize == 16 || EltSize % 32 == 0; in isRegisterVectorElementType()
196 return EltSize == 32 || EltSize == 64 || in isRegisterVectorType()
198 EltSize == 128 || EltSize == 256; in isRegisterVectorType()
351 unsigned EltSize = EltTy.getSizeInBits(); in loadStoreBitcastWorkaround() local
352 return EltSize != 32 && EltSize != 64; in loadStoreBitcastWorkaround()
1440 return (EltSize == 32 || EltSize == 64) && in AMDGPULegalizerInfo()
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H A DAMDGPUTargetTransformInfo.cpp796 unsigned EltSize in getVectorInstrCost() local
798 if (EltSize < 32) { in getVectorInstrCost()
799 if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) in getVectorInstrCost()
H A DSIRegisterInfo.h299 unsigned EltSize) const;
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuilder.h217 CharUnits EltSize = variable
224 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
236 CharUnits EltSize = CharUnits::fromQuantity(DL.getTypeAllocSize(ElTy)); variable
241 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
252 CharUnits EltSize = variable
258 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
267 CharUnits EltSize = variable
273 Addr.getAlignment().alignmentOfArrayElement(EltSize));
H A DCGNonTrivialStruct.cpp196 CharUnits EltSize = Ctx.getTypeSizeInChars(EltTy); in visitArray() local
198 llvm::to_string(EltSize.getQuantity()) + "n" + in visitArray()
398 CharUnits EltSize = Ctx.getTypeSizeInChars(EltQT); in visitArray() local
404 StartAddrs[I].getAlignment().alignmentAtOffset(EltSize)); in visitArray()
415 NewAddrs[I] = getAddrWithOffset(NewAddrs[I], EltSize); in visitArray()
H A DCGDecl.cpp1752 CharUnits EltSize = getContext().getTypeSizeInChars(VlaSize.Type); in emitZeroOrPatternForAutoVarInit() local
1760 if (!EltSize.isOne()) in emitZeroOrPatternForAutoVarInit()
1761 SizeVal = Builder.CreateNUWMul(SizeVal, CGM.getSize(EltSize)); in emitZeroOrPatternForAutoVarInit()
1783 if (!EltSize.isOne()) in emitZeroOrPatternForAutoVarInit()
1784 SizeVal = Builder.CreateNUWMul(SizeVal, CGM.getSize(EltSize)); in emitZeroOrPatternForAutoVarInit()
1786 llvm::ConstantInt::get(IntPtrTy, EltSize.getQuantity()); in emitZeroOrPatternForAutoVarInit()
1794 CharUnits CurAlign = Loc.getAlignment().alignmentOfArrayElement(EltSize); in emitZeroOrPatternForAutoVarInit()
H A DTargetInfo.cpp3371 unsigned EltOffset = i*EltSize; in BitsContainNoUserData()
3452 unsigned EltSize = TD.getTypeAllocSize(EltTy); in getFPTypeAtOffset() local
3453 IROffset -= IROffset / EltSize * EltSize; in getFPTypeAtOffset()
3566 unsigned EltOffset = IROffset/EltSize*EltSize; in GetINTEGERTypeAtOffset()
4689 CharUnits EltSize = TypeInfo.Width / 2; in EmitVAArg() local
4690 if (EltSize < SlotSize) in EmitVAArg()
5465 CharUnits EltSize = TypeInfo.Width / 2; in EmitVAArg() local
5466 if (EltSize < SlotSize) in EmitVAArg()
9120 if (EltSize == 16) in numRegsForType()
9123 unsigned EltNumRegs = (EltSize + 31) / 32; in numRegsForType()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp66 static bool isREVMask(ArrayRef<int> M, unsigned EltSize, unsigned NumElts, in isREVMask() argument
70 assert(EltSize != 64 && "EltSize cannot be 64 for REV mask."); in isREVMask()
76 BlockElts = BlockSize / EltSize; in isREVMask()
78 if (BlockSize <= EltSize || BlockSize != BlockElts * EltSize) in isREVMask()
225 unsigned EltSize = Ty.getScalarSizeInBits(); in matchREV() local
228 if (EltSize == 64) in matchREV()
234 if (isREVMask(ShuffleMask, EltSize, NumElts, 64)) { in matchREV()
923 unsigned EltSize = MRI.getType(LHS).getScalarSizeInBits(); in lowerVectorFCMP() local
924 if (EltSize != 32 && EltSize != 64) in lowerVectorFCMP()
H A DAArch64InstructionSelector.cpp2494 if (EltSize == 32) in select()
2497 else if (EltSize == 64) in select()
3960 switch (EltSize) { in emitScalarToVector()
4045 switch (EltSize) { in getLaneCopyOpcode()
4401 if (EltSize == 16) { in getInsertVecEltOpInfo()
4404 } else if (EltSize == 32) { in getInsertVecEltOpInfo()
4407 } else if (EltSize == 64) { in getInsertVecEltOpInfo()
4414 if (EltSize == 8) { in getInsertVecEltOpInfo()
4417 } else if (EltSize == 16) { in getInsertVecEltOpInfo()
5315 if (EltSize < 16 || EltSize > 64) in selectInsertElt()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h313 unsigned EltSize = DataTypeVTy->getElementType()->getScalarSizeInBits(); in isLegalNTStore() local
314 return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 && in isLegalNTStore()
315 EltSize <= 128 && isPowerOf2_64(EltSize); in isLegalNTStore()
H A DAArch64RegisterInfo.td1273 class MatrixTileAsmOperand<string RC, int EltSize> : AsmOperandClass {
1274 let Name = "MatrixTile" # EltSize;
1280 # EltSize # ", AArch64::" # RC # "RegClassID>";
1297 class MatrixTileVectorAsmOperand<string RC, int EltSize, int IsVertical>
1299 let Name = "MatrixTileVector" # !if(IsVertical, "V", "H") # EltSize;
1306 # EltSize # ", AArch64::" # RC # "RegClassID>";
1309 class MatrixTileVectorOperand<int EltSize, int NumBitsForTile,
1334 class MatrixAsmOperand<string RC, int EltSize> : AsmOperandClass {
1341 # EltSize # ", AArch64::" # RC # "RegClassID>";
1345 let ParserMatchClass = MatrixAsmOperand<!cast<string>(RC), EltSize>;
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H A DAArch64StackTagging.cpp282 uint32_t EltSize = DL->getTypeSizeInBits(EltTy); in flatten() local
284 IntegerType::get(Ctx, EltSize), in flatten()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DLoads.cpp272 APInt EltSize(DL.getIndexTypeSizeInBits(Ptr->getType()), in isDereferenceableAndAlignedInLoop() local
281 return isDereferenceableAndAlignedPointer(Ptr, Alignment, EltSize, DL, in isDereferenceableAndAlignedInLoop()
293 if (Step->getAPInt() != EltSize) in isDereferenceableAndAlignedInLoop()
300 const APInt AccessSize = TC * EltSize; in isDereferenceableAndAlignedInLoop()
311 if (EltSize.urem(Alignment.value()) != 0) in isDereferenceableAndAlignedInLoop()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4258 unsigned EltSize = MemIntr->getMemoryVT().getSizeInBits(); in matchVPTERNLOG() local
4259 assert((EltSize == 32 || EltSize == 64) && "Unexpected broadcast size!"); in matchVPTERNLOG()
4261 bool UseD = EltSize == 32; in matchVPTERNLOG()
5928 unsigned EltSize = ValueSVT.getSizeInBits(); in Select() local
5933 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) in Select()
5960 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) in Select()
6024 unsigned EltSize = ValueSVT.getSizeInBits(); in Select() local
6027 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) in Select()
6029 else if (IndexVT == MVT::v8i32 && NumElts == 8 && EltSize == 32) in Select()
6033 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64) in Select()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp104 uint64_t EltSize = DL.getTypeAllocSize(EltTy).getFixedValue(); in ComputeValueVTs() local
107 StartingOffset + i * EltSize); in ComputeValueVTs()
149 uint64_t EltSize = DL.getTypeAllocSize(EltTy).getFixedValue(); in computeValueLLTs() local
152 StartingOffset + i * EltSize); in computeValueLLTs()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp312 const unsigned EltSize = DL.getTypeSizeInBits(Ty->getElementType()); in getMaxVLFor() local
315 return RISCVTargetLowering::computeVLMAX(VectorBitsMax, EltSize, MinSize); in getMaxVLFor()
H A DRISCVISelLowering.h567 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, in computeVLMAX() argument
574 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock; in computeVLMAX()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1570 unsigned EltSize = VTy->getScalarSizeInBits(); in getGatherScatterOpCost() local
1586 if (EltSize < 8 || Alignment < EltSize / 8) in getGatherScatterOpCost()
1589 unsigned ExtSize = EltSize; in getGatherScatterOpCost()
1603 if (((TypeSize == 32 && (EltSize == 8 || EltSize == 16)) || in getGatherScatterOpCost()
1604 (TypeSize == 16 && EltSize == 8)) && in getGatherScatterOpCost()
1617 if (((EltSize == 16 && TypeSize == 32) || in getGatherScatterOpCost()
1618 (EltSize == 8 && (TypeSize == 32 || TypeSize == 16))) && in getGatherScatterOpCost()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineLoadStoreAlloca.cpp695 auto EltSize = DL.getTypeAllocSize(ET); in unpackLoadToAggregate() local
716 Offset += EltSize; in unpackLoadToAggregate()
1214 auto EltSize = DL.getTypeAllocSize(AT->getElementType()); in unpackStoreToAggregate() local
1238 Offset += EltSize; in unpackStoreToAggregate()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h201 template <int EltSize>

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