108     unsigned EltSize;  member
220   unsigned read2Opcode(unsigned EltSize) const;
221   unsigned read2ST64Opcode(unsigned EltSize) const;
226   unsigned write2Opcode(unsigned EltSize) const;
227   unsigned write2ST64Opcode(unsigned EltSize) const;
654    EltSize =  in setMI()
659     EltSize =  in setMI()
664     EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4);  in setMI()
667     EltSize = 4;  in setMI()
878   if ((CI.Offset % CI.EltSize != 0) || (Paired.Offset % CI.EltSize != 0))  in offsetsCanBeCombined()
905   uint32_t EltOffset0 = CI.Offset / CI.EltSize;  in offsetsCanBeCombined()
906   uint32_t EltOffset1 = Paired.Offset / CI.EltSize;  in offsetsCanBeCombined()
952       CI.BaseOff = BaseOff * CI.EltSize;  in offsetsCanBeCombined()
966       CI.BaseOff = BaseOff * CI.EltSize;  in offsetsCanBeCombined()
1070 unsigned SILoadStoreOptimizer::read2Opcode(unsigned EltSize) const {  in read2Opcode()
1072     return (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64;  in read2Opcode()
1073   return (EltSize == 4) ? AMDGPU::DS_READ2_B32_gfx9 : AMDGPU::DS_READ2_B64_gfx9;  in read2Opcode()
1076 unsigned SILoadStoreOptimizer::read2ST64Opcode(unsigned EltSize) const {  in read2ST64Opcode()
1078     return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64;  in read2ST64Opcode()
1080   return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32_gfx9  in read2ST64Opcode()
1099       CI.UseST64 ? read2ST64Opcode(CI.EltSize) : read2Opcode(CI.EltSize);  in mergeRead2Pair()
1101   unsigned SubRegIdx0 = (CI.EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1;  in mergeRead2Pair()
1102   unsigned SubRegIdx1 = (CI.EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3;  in mergeRead2Pair()
1165 unsigned SILoadStoreOptimizer::write2Opcode(unsigned EltSize) const {  in write2Opcode()
1167     return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64;  in write2Opcode()
1168   return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32_gfx9  in write2Opcode()
1172 unsigned SILoadStoreOptimizer::write2ST64Opcode(unsigned EltSize) const {  in write2ST64Opcode()
1174     return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32  in write2ST64Opcode()
1177   return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32_gfx9  in write2ST64Opcode()
1198       CI.UseST64 ? write2ST64Opcode(CI.EltSize) : write2Opcode(CI.EltSize);  in mergeWrite2Pair()