142   MachineInstr *emitScalarToVector(unsigned EltSize,
2493     unsigned EltSize = DstTy.getElementType().getSizeInBits();  in select()  local
2494     if (EltSize == 32)  in select()
2497     else if (EltSize == 64)  in select()
3946     unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar,  in emitScalarToVector()  argument
3960   switch (EltSize) {  in emitScalarToVector()
4042                               const unsigned EltSize) {  in getLaneCopyOpcode()  argument
4045   switch (EltSize) {  in getLaneCopyOpcode()
4064     LLVM_DEBUG(dbgs() << "Elt size '" << EltSize << "' unsupported.\n");  in getLaneCopyOpcode()
4398 getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {  in getInsertVecEltOpInfo()  argument
4401     if (EltSize == 16) {  in getInsertVecEltOpInfo()
4404     } else if (EltSize == 32) {  in getInsertVecEltOpInfo()
4407     } else if (EltSize == 64) {  in getInsertVecEltOpInfo()
4414     if (EltSize == 8) {  in getInsertVecEltOpInfo()
4417     } else if (EltSize == 16) {  in getInsertVecEltOpInfo()
4420     } else if (EltSize == 32) {  in getInsertVecEltOpInfo()
4423     } else if (EltSize == 64) {  in getInsertVecEltOpInfo()
5218   unsigned EltSize = MRI.getType(EltReg).getSizeInBits();  in emitLaneInsert()  local
5219   unsigned Opc = getInsertVecEltOpInfo(RB, EltSize).first;  in emitLaneInsert()
5222     auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder);  in emitLaneInsert()
5314   unsigned EltSize = EltTy.getSizeInBits();  in selectInsertElt()  local
5315   if (EltSize < 16 || EltSize > 64)  in selectInsertElt()
5493   unsigned EltSize = EltTy.getSizeInBits();  in selectBuildVector()  local
5500   if (EltSize < 16 || EltSize > 64)  in selectBuildVector()
5517   for (unsigned i = 2, e = DstSize / EltSize + 1; i < e; ++i) {  in selectBuildVector()