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Searched refs:DstReg (Results 1 – 25 of 134) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp659 if (DstReg == SrcReg) in expand()
779 if (DstReg == SrcReg) in expand()
836 if (DstReg == SrcReg) in expandLPMWELPMW()
1194 .addReg(DstReg) in expand()
1376 .addReg(DstReg, RegState::Kill) in expand()
1411 buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg); in expand()
1414 buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7); in expand()
2092 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd()
2098 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd()
2142 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
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H A DAVRRegisterInfo.cpp113 Register DstReg) { in foldFrameOffset() argument
124 if (DstReg != MI.getOperand(0).getReg()) { in foldFrameOffset()
177 Register DstReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
178 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer"); in eliminateFrameIndex()
191 foldFrameOffset(II, Offset, DstReg); in eliminateFrameIndex()
194 switch (DstReg) { in eliminateFrameIndex()
212 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg) in eliminateFrameIndex()
213 .addReg(DstReg, RegState::Kill) in eliminateFrameIndex()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp233 Register DstReg; in movImm() local
250 .addReg(DstReg) in movImm()
266 .addReg(DstReg) in movImm()
271 .addReg(DstReg) in movImm()
279 .addReg(DstReg) in movImm()
284 .addReg(DstReg) in movImm()
288 .addReg(DstReg) in movImm()
301 .addReg(DstReg) in movImm()
310 .addReg(DstReg) in movImm()
319 .addReg(DstReg) in movImm()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h75 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
88 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
101 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
126 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
151 UpdatedDefs.push_back(DstReg); in tryCombineZExt()
164 UpdatedDefs.push_back(DstReg); in tryCombineZExt()
185 LLT DstTy = MRI.getType(DstReg); in tryCombineSExt()
207 UpdatedDefs.push_back(DstReg); in tryCombineSExt()
323 UpdatedDefs.push_back(DstReg); in tryCombineTrunc()
523 UpdatedDefs.push_back(DstReg); in replaceRegOrBuildCopy()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
279 if (Hexagon::R31 == DstReg) in getDuplexCandidateGroup()
419 if (DstReg == SrcReg) { in getDuplexCandidateGroup()
435 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) && in getDuplexCandidateGroup()
483 if (Hexagon::P0 == DstReg && in getDuplexCandidateGroup()
536 unsigned DstReg, SrcReg; in subInstWouldBeExtended() local
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H A DHexagonMCCompound.cpp81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
97 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
111 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
113 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
123 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
125 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getCompoundCandidateGroup()
133 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
136 HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) in getCompoundCandidateGroup()
142 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp135 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
138 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
142 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
155 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
157 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
172 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
174 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
183 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
186 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
190 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp244 if (DstReg.isPhysical()) { in selectCopy()
718 const LLT DstTy = MRI.getType(DstReg); in selectTruncOrPtrToInt()
782 const LLT DstTy = MRI.getType(DstReg); in selectZext()
847 const LLT DstTy = MRI.getType(DstReg); in selectAnyext()
885 .addDef(DstReg) in selectAnyext()
1047 const LLT DstTy = MRI.getType(DstReg); in selectUadde()
1105 const LLT DstTy = MRI.getType(DstReg); in selectExtract()
1156 const LLT DstTy = MRI.getType(DstReg); in emitExtractSubreg()
1456 if (!MRI.getRegClassOrNull(DstReg)) { in selectImplicitDefOrPHI()
1662 .addDef(DstReg) in selectDivRem()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.cpp512 if (isLaneMaskReg(DstReg) || isVreg1(DstReg)) in lowerCopiesFromI1()
572 Register DstReg = MI->getOperand(0).getReg(); in lowerPhis() local
598 PhiRegisters.insert(DstReg); in lowerPhis()
616 SSAUpdater.Initialize(DstReg); in lowerPhis()
664 if (NewReg != DstReg) { in lowerPhis()
665 MRI->replaceRegWith(NewReg, DstReg); in lowerPhis()
691 if (!isVreg1(DstReg)) in lowerCopiesToI1()
696 if (MRI->use_empty(DstReg)) { in lowerCopiesToI1()
732 SSAUpdater.Initialize(DstReg); in lowerCopiesToI1()
736 buildMergeLaneMasks(MBB, MI, DL, DstReg, in lowerCopiesToI1()
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H A DR600ExpandSpecialInstrs.cpp126 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
127 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
130 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
196 Register DstReg = in runOnMachineFunction() local
226 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
230 Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
231 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
232 DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); in runOnMachineFunction()
252 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
H A DAMDGPUInstructionSelector.cpp126 Register DstReg = Dst.getReg(); in selectCOPY() local
129 if (isVCC(DstReg, *MRI)) { in selectCOPY()
309 LLT Ty = MRI->getType(DstReg); in selectG_ADD_SUB()
484 LLT DstTy = MRI->getType(DstReg); in selectG_EXTRACT()
528 LLT DstTy = MRI->getType(DstReg); in selectG_MERGE_VALUES()
1266 Register DstReg = Dst.getReg(); in selectReturnAddress() local
1923 const LLT DstTy = MRI->getType(DstReg); in selectG_TRUNC()
2069 const LLT DstTy = MRI->getType(DstReg); in selectG_SZA_EXT()
2550 LLT Ty = MRI->getType(DstReg); in selectG_PTRMASK()
2688 LLT DstTy = MRI->getType(DstReg); in selectG_EXTRACT_VECTOR_ELT()
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H A DSIFixSGPRCopies.cpp152 Register DstReg = Copy.getOperand(0).getReg(); in getCopyRegClasses() local
188 Register DstReg = MI.getOperand(0).getReg(); in tryChangeVGPRtoSGPRinCopy() local
190 if (!SrcReg.isVirtual() || !DstReg.isVirtual()) in tryChangeVGPRtoSGPRinCopy()
207 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
230 Register DstReg = MI.getOperand(0).getReg(); in foldVGPRCopyIntoRegSequence() local
231 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
234 if (!MRI.hasOneUse(DstReg)) in foldVGPRCopyIntoRegSequence()
259 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
625 } else if (DstReg == AMDGPU::SCC) { in runOnMachineFunction()
641 if (!DstReg.isVirtual()) { in runOnMachineFunction()
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/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp28 const DebugLoc &DL, MCRegister DstReg, in copyPhysReg() argument
30 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
31 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg) in copyPhysReg()
39 if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
41 } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
48 BuildMI(MBB, MBBI, DL, get(Opc), DstReg) in copyPhysReg()
86 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DstReg, in loadRegFromStackSlot() argument
111 BuildMI(MBB, I, DL, get(Opcode), DstReg) in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp67 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
170 Register &DstReg, const GlobalValue *GVal, bool IsAma) { in processCandidate() argument
171 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
179 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processCandidate()
189 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma); in processCandidate()
194 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg) in processCandidate()
200 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate()
204 Register &DstReg, Register &SrcReg, const GlobalValue *GVal, in processDstReg() argument
206 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processDstReg()
284 Register DstReg = MI.getOperand(0).getReg(); in removeLD() local
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp122 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
127 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { in expandMOVImm()
158 .addReg(DstReg, RegState::Define | in expandMOVImm()
169 .addReg(DstReg, in expandMOVImm()
173 .addReg(DstReg) in expandMOVImm()
908 .addReg(DstReg, in expandMI()
917 .addReg(DstReg, in expandMI()
1081 .addUse(DstReg) in expandMI()
1097 assert(DstReg != AArch64::XZR); in expandMI()
1114 .addReg(DstReg) in expandMI()
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H A DAArch64RedundantCopyElimination.cpp186 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
195 SrcReg != DstReg) { in knownRegValInBlock()
209 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
214 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
218 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
252 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
253 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
258 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
263 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp69 Register DstReg = MI->getOperand(0).getReg(); in TransferImplicitOperands() local
76 if (MO.isKill() && TRI->regsOverlap(DstReg, MO.getReg())) in TransferImplicitOperands()
88 Register DstReg = MI->getOperand(0).getReg(); in LowerSubregToReg() local
94 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
96 assert(Register::isPhysicalRegister(DstReg) && in LowerSubregToReg()
116 if (DstReg != InsReg) { in LowerSubregToReg()
131 CopyMI->addRegisterDefined(DstReg); in LowerSubregToReg()
H A DTwoAddressInstructionPass.cpp154 void scanUses(Register DstReg);
272 DstReg = 0; in isCopyToReg()
350 Register SrcReg, DstReg; in isKilled() local
728 Register Reg = DstReg; in scanUses()
781 Register SrcReg, DstReg; in processCopy() local
793 scanUses(DstReg); in processCopy()
841 Register DstReg; in rescheduleMIBelowKill() local
1026 Register DstReg; in rescheduleKillAboveMI() local
1425 if (SrcReg == DstReg) in collectTiedOperands()
1433 if (DstReg.isVirtual()) { in collectTiedOperands()
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H A DOptimizePHIs.cpp100 Register DstReg = MI->getOperand(0).getReg(); in IsSingleValuePHICycle() local
113 if (SrcReg == DstReg) in IsSingleValuePHICycle()
144 Register DstReg = MI->getOperand(0).getReg(); in IsDeadPHICycle() local
145 assert(Register::isVirtualRegister(DstReg) && in IsDeadPHICycle()
156 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) { in IsDeadPHICycle()
H A DRegisterCoalescer.h33 Register DstReg; variable
66 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {} in CoalescerPair()
97 Register getDstReg() const { return DstReg; } in getDstReg()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp169 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
176 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction()
179 assert(canReplaceReg(DstReg, SrcReg, MRI) && in runOnMachineFunction()
182 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
231 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
233 Register::isVirtualRegister(DstReg)) { in runOnMachineFunction()
235 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction()
237 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp634 if (M68k::XR32RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
642 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg()
655 if (M68k::XR16RegClass.contains(DstReg)) in copyPhysReg()
657 else if (M68k::XR32RegClass.contains(DstReg)) in copyPhysReg()
660 M68k::XR32RegClass.contains(DstReg)) in copyPhysReg()
664 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg()
671 bool ToCCR = DstReg == M68k::CCR; in copyPhysReg()
672 bool ToSR = DstReg == M68k::SR; in copyPhysReg()
675 assert(M68k::DR8RegClass.contains(DstReg) && in copyPhysReg()
686 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3141 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3163 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3166 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3169 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
4461 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4464 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4559 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSge()
4696 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSle()
4744 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSleImm()
5195 DstReg, DstReg, 0x1F, IDLoc, STI); in expandMulO()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp122 return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs; in forwardCopyWillClobberTuple()
260 if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
261 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) in copyPhysReg()
269 RISCV::GPRRegClass.contains(DstReg)) { in copyPhysReg()
448 BuildMI(MBB, MBBI, DL, get(Opc), DstReg) in copyPhysReg()
633 BuildMI(MBB, I, DL, get(Opcode), DstReg) in loadRegFromStackSlot()
690 Register DstReg = MI.getOperand(0).getReg(); in foldMemoryOperandImpl() local
692 DstReg) in foldMemoryOperandImpl()
714 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg) in movImm()
719 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg) in movImm()
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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp79 Register DstReg = MI->getOperand(0).getReg(); in visitMBB() local
80 if (DstReg.isVirtual() && in visitMBB()
91 SystemZ::AR32BitRegClass.contains(DstReg)) { in visitMBB()
94 BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp); in visitMBB()

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