152   Register DstReg = Copy.getOperand(0).getReg();  in getCopyRegClasses()  local
162   const TargetRegisterClass *DstRC = DstReg.isVirtual()  in getCopyRegClasses()
163                                          ? MRI.getRegClass(DstReg)  in getCopyRegClasses()
164                                          : TRI.getPhysRegClass(DstReg);  in getCopyRegClasses()
188   Register DstReg = MI.getOperand(0).getReg();  in tryChangeVGPRtoSGPRinCopy()  local
190   if (!SrcReg.isVirtual() || !DstReg.isVirtual())  in tryChangeVGPRtoSGPRinCopy()
193   for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) {  in tryChangeVGPRtoSGPRinCopy()
207   MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));  in tryChangeVGPRtoSGPRinCopy()
230   Register DstReg = MI.getOperand(0).getReg();  in foldVGPRCopyIntoRegSequence()  local
231   if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))  in foldVGPRCopyIntoRegSequence()
234   if (!MRI.hasOneUse(DstReg))  in foldVGPRCopyIntoRegSequence()
237   MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);  in foldVGPRCopyIntoRegSequence()
259   MRI.setRegClass(DstReg, DstRC);  in foldVGPRCopyIntoRegSequence()
603         Register DstReg = MI.getOperand(0).getReg();  in runOnMachineFunction()  local
621                         TII->get(AMDGPU::COPY), DstReg)  in runOnMachineFunction()
625           } else if (DstReg == AMDGPU::SCC) {  in runOnMachineFunction()
641         if (!DstReg.isVirtual()) {  in runOnMachineFunction()
646           if (DstReg == AMDGPU::M0 && TRI->hasVectorRegisters(SrcRC)) {  in runOnMachineFunction()
1033       Register DstReg = MI.getOperand(0).getReg();  in lowerVGPR2SGPRCopies()  local
1035       const TargetRegisterClass *DstRC = TRI->getRegClassForReg(*MRI, DstReg);  in lowerVGPR2SGPRCopies()
1132     Register DstReg = MI->getOperand(0).getReg();  in lowerVGPR2SGPRCopies()  local
1141                          TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg);  in lowerVGPR2SGPRCopies()
1145                          TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg);  in lowerVGPR2SGPRCopies()
1149                             TII->get(AMDGPU::REG_SEQUENCE), DstReg);  in lowerVGPR2SGPRCopies()