Lines Matching refs:DstReg
88 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
507 Register DstReg = MI.getOperand(0).getReg(); in lowerCopiesFromI1() local
512 if (isLaneMaskReg(DstReg) || isVreg1(DstReg)) in lowerCopiesFromI1()
521 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg)); in lowerCopiesFromI1()
525 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in lowerCopiesFromI1()
572 Register DstReg = MI->getOperand(0).getReg(); in lowerPhis() local
573 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
598 PhiRegisters.insert(DstReg); in lowerPhis()
604 for (MachineInstr &Use : MRI->use_instructions(DstReg)) in lowerPhis()
616 SSAUpdater.Initialize(DstReg); in lowerPhis()
664 if (NewReg != DstReg) { in lowerPhis()
665 MRI->replaceRegWith(NewReg, DstReg); in lowerPhis()
690 Register DstReg = MI.getOperand(0).getReg(); in lowerCopiesToI1() local
691 if (!isVreg1(DstReg)) in lowerCopiesToI1()
696 if (MRI->use_empty(DstReg)) { in lowerCopiesToI1()
703 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerCopiesToI1()
725 for (MachineInstr &Use : MRI->use_instructions(DstReg)) in lowerCopiesToI1()
732 SSAUpdater.Initialize(DstReg); in lowerCopiesToI1()
733 SSAUpdater.AddAvailableValue(&MBB, DstReg); in lowerCopiesToI1()
736 buildMergeLaneMasks(MBB, MI, DL, DstReg, in lowerCopiesToI1()
830 const DebugLoc &DL, unsigned DstReg, in buildMergeLaneMasks() argument
839 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg); in buildMergeLaneMasks()
841 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg); in buildMergeLaneMasks()
843 BuildMI(MBB, I, DL, TII->get(XorOp), DstReg) in buildMergeLaneMasks()
875 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg) in buildMergeLaneMasks()
878 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg) in buildMergeLaneMasks()
881 BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg) in buildMergeLaneMasks()
885 BuildMI(MBB, I, DL, TII->get(OrOp), DstReg) in buildMergeLaneMasks()