120 static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,  in forwardCopyWillClobberTuple()  argument
122   return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs;  in forwardCopyWillClobberTuple()
258                                  const DebugLoc &DL, MCRegister DstReg,  in copyPhysReg()  argument
260   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
261     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)  in copyPhysReg()
269       RISCV::GPRRegClass.contains(DstReg)) {  in copyPhysReg()
271     BuildMI(MBB, MBBI, DL, get(RISCV::CSRRS), DstReg)  in copyPhysReg()
283   if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
286   } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
289   } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
292   } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
295   } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
298   } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
301   } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
304   } else if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
309   } else if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
314   } else if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
319   } else if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
324   } else if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
329   } else if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
334   } else if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
339   } else if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
344   } else if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
349   } else if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
354   } else if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
402       auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);  in copyPhysReg()
420       unsigned DstEncoding = TRI->getEncodingValue(DstReg);  in copyPhysReg()
433                            TRI->getSubReg(DstReg, SubRegIdx + I));  in copyPhysReg()
448     BuildMI(MBB, MBBI, DL, get(Opc), DstReg)  in copyPhysReg()
550                                           Register DstReg, int FI,  in loadRegFromStackSlot()  argument
619     auto MIB = BuildMI(MBB, I, DL, get(Opcode), DstReg)  in loadRegFromStackSlot()
633     BuildMI(MBB, I, DL, get(Opcode), DstReg)  in loadRegFromStackSlot()
690   Register DstReg = MI.getOperand(0).getReg();  in foldMemoryOperandImpl()  local
692                  DstReg)  in foldMemoryOperandImpl()
700                             const DebugLoc &DL, Register DstReg, uint64_t Val,  in movImm()  argument
714       BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)  in movImm()
719       BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)  in movImm()
725       BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)  in movImm()
731       BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)  in movImm()
739     SrcReg = DstReg;  in movImm()