Lines Matching refs:DstReg
230 bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
234 bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
252 bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
2182 MCOperand &DstReg = Inst.getOperand(0); in processInstruction() local
2186 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) && in processInstruction()
2190 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset, in processInstruction()
2698 bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, in loadImmediate() argument
2728 unsigned TmpReg = DstReg; in loadImmediate()
2730 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { in loadImmediate()
2747 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2751 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2756 unsigned TmpReg = DstReg; in loadImmediate()
2757 if (SrcReg == DstReg) { in loadImmediate()
2765 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2781 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2792 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2800 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2820 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2857 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2876 bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg, in expandLoadAddress() argument
2895 return loadAndAddSymbolAddress(Offset.getExpr(), DstReg, BaseReg, in expandLoadAddress()
2903 return loadImmediate(Offset.getImm(), DstReg, BaseReg, Is32BitAddress, true, in expandLoadAddress()
2908 unsigned DstReg, unsigned SrcReg, in loadAndAddSymbolAddress() argument
2941 if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg && in loadAndAddSymbolAddress()
2948 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
2950 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg, in loadAndAddSymbolAddress()
2952 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg, in loadAndAddSymbolAddress()
2957 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg, in loadAndAddSymbolAddress()
2963 unsigned TmpReg = DstReg; in loadAndAddSymbolAddress()
2965 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, in loadAndAddSymbolAddress()
3007 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3072 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3098 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg); in loadAndAddSymbolAddress()
3121 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3124 } else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) { in loadAndAddSymbolAddress()
3138 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3141 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3145 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
3146 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI); in loadAndAddSymbolAddress()
3148 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3152 (canUseATReg() && DstReg == getATReg(IDLoc))) { in loadAndAddSymbolAddress()
3161 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3163 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3165 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3166 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3168 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3169 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3172 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3178 assert(SrcReg == DstReg && !canUseATReg() && in loadAndAddSymbolAddress()
3195 unsigned TmpReg = DstReg; in loadAndAddSymbolAddress()
3197 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { in loadAndAddSymbolAddress()
3211 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3214 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg)); in loadAndAddSymbolAddress()
3691 unsigned DstReg = DstRegOp.getReg(); in expandMem16Inst() local
3693 unsigned TmpReg = DstReg; in expandMem16Inst()
3702 if (!IsLoad || !IsGPR || (BaseReg == DstReg)) { in expandMem16Inst()
3712 TOut.emitRRX(OpCode, DstReg, TmpReg, Off, IDLoc, STI); in expandMem16Inst()
3714 TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, Off, IDLoc, STI); in expandMem16Inst()
3818 unsigned DstReg = DstRegOp.getReg(); in expandMem9Inst() local
3820 unsigned TmpReg = DstReg; in expandMem9Inst()
3829 if (!IsLoad || !IsGPR || (BaseReg == DstReg)) { in expandMem9Inst()
3839 TOut.emitRRX(OpCode, DstReg, TmpReg, MCOperand::createImm(0), IDLoc, STI); in expandMem9Inst()
3841 TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, MCOperand::createImm(0), in expandMem9Inst()
4386 unsigned DstReg = DstRegOp.getReg(); in expandUlh() local
4409 unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg; in expandUlh()
4410 unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg; in expandUlh()
4413 unsigned SllReg = IsLargeOffset ? DstReg : ATReg; in expandUlh()
4419 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUlh()
4438 unsigned DstReg = DstRegOp.getReg(); in expandUsh() local
4460 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI); in expandUsh()
4461 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4462 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI); in expandUsh()
4464 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4465 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUsh()
4467 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI); in expandUsh()
4468 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI); in expandUsh()
4489 unsigned DstReg = DstRegOp.getReg(); in expandUxw() local
4501 bool DoMove = IsLoadInst && (SrcReg == DstReg) && !IsLargeOffset; in expandUxw()
4517 std::swap(DstReg, TmpReg); in expandUxw()
4521 TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI); in expandUxw()
4522 TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI); in expandUxw()
4525 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI); in expandUxw()
4539 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSge() local
4558 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
4559 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSge()
4573 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSgeImm() local
4598 TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI); in expandSgeImm()
4599 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4601 unsigned ImmReg = DstReg; in expandSgeImm()
4602 if (DstReg == SrcReg) { in expandSgeImm()
4613 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI); in expandSgeImm()
4614 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4629 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSgtImm() local
4631 unsigned ImmReg = DstReg; in expandSgtImm()
4650 if (DstReg == SrcReg) { in expandSgtImm()
4662 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSgtImm()
4676 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSle() local
4695 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); in expandSle()
4696 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSle()
4710 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSleImm() local
4731 unsigned ImmReg = DstReg; in expandSleImm()
4732 if (DstReg == SrcReg) { in expandSleImm()
4743 TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSleImm()
4744 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSleImm()
4761 unsigned DstReg = Inst.getOperand(0).getReg(); in expandAliasImmediate() local
4769 if (DstReg == SrcReg) { in expandAliasImmediate()
4773 FinalDstReg = DstReg; in expandAliasImmediate()
4774 DstReg = ATReg; in expandAliasImmediate()
4777 if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, in expandAliasImmediate()
4848 TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI); in expandAliasImmediate()
4850 TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI); in expandAliasImmediate()
5158 unsigned DstReg = Inst.getOperand(0).getReg(); in expandMulImm() local
5172 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
5181 unsigned DstReg = Inst.getOperand(0).getReg(); in expandMulO() local
5192 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5195 DstReg, DstReg, 0x1F, IDLoc, STI); in expandMulO()
5200 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); in expandMulO()
5207 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI); in expandMulO()
5214 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5223 unsigned DstReg = Inst.getOperand(0).getReg(); in expandMulOU() local
5235 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
5258 unsigned DstReg = Inst.getOperand(0).getReg(); in expandDMULMacro() local
5263 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
5367 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSeq() local
5374 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5375 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeq()
5380 TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI); in expandSeq()
5393 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSeqI() local
5400 TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI); in expandSeqI()
5407 DstReg, SrcReg, SrcReg, IDLoc, STI); in expandSeqI()
5428 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSeqI()
5429 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5433 TOut.emitRRI(Opc, DstReg, SrcReg, Imm, IDLoc, STI); in expandSeqI()
5434 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5448 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSne() local
5455 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSne()
5456 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSne()
5461 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); in expandSne()
5474 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSneI() local
5481 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI); in expandSneI()
5487 if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out, in expandSneI()
5502 TOut.emitRRI(Opc, DstReg, SrcReg, ImmValue, IDLoc, STI); in expandSneI()
5503 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5515 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSneI()
5516 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()