Lines Matching refs:DstReg
126 Register DstReg = Dst.getReg(); in selectCOPY() local
129 if (isVCC(DstReg, *MRI)) { in selectCOPY()
135 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
140 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
151 BuildMI(*BB, &I, DL, TII.get(MovOpc), DstReg) in selectCOPY()
165 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg) in selectCOPY()
178 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
242 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64() local
247 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg) in getSubOperand64()
250 return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(), in getSubOperand64()
284 Register DstReg = I.getOperand(0).getReg(); in selectG_AND_OR_XOR() local
285 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
287 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
307 Register DstReg = I.getOperand(0).getReg(); in selectG_ADD_SUB() local
309 LLT Ty = MRI->getType(DstReg); in selectG_ADD_SUB()
314 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB()
322 BuildMI(*BB, &I, DL, TII.get(Opc), DstReg) in selectG_ADD_SUB()
341 = BuildMI(*BB, &I, DL, TII.get(Opc), DstReg) in selectG_ADD_SUB()
391 BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg) in selectG_ADD_SUB()
398 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI)) in selectG_ADD_SUB()
482 Register DstReg = I.getOperand(0).getReg(); in selectG_EXTRACT() local
484 LLT DstTy = MRI->getType(DstReg); in selectG_EXTRACT()
501 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_EXTRACT()
518 BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY), DstReg) in selectG_EXTRACT()
527 Register DstReg = MI.getOperand(0).getReg(); in selectG_MERGE_VALUES() local
528 LLT DstTy = MRI->getType(DstReg); in selectG_MERGE_VALUES()
536 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES()
545 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::REG_SEQUENCE), DstReg); in selectG_MERGE_VALUES()
557 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_MERGE_VALUES()
731 Register DstReg = I.getOperand(0).getReg(); in selectG_INSERT() local
736 unsigned DstSize = MRI->getType(DstReg).getSizeInBits(); in selectG_INSERT()
753 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_INSERT()
772 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || in selectG_INSERT()
778 BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG), DstReg) in selectG_INSERT()
788 Register DstReg = MI.getOperand(0).getReg(); in selectG_SBFX_UBFX() local
793 assert(RBI.getRegBank(DstReg, *MRI, TRI)->getID() == AMDGPU::VGPRRegBankID && in selectG_SBFX_UBFX()
803 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg) in selectG_SBFX_UBFX()
967 Register DstReg = I.getOperand(0).getReg(); in selectG_INTRINSIC() local
973 for (Register Reg : { DstReg, Src0Reg, Src1Reg }) in selectG_INTRINSIC()
1180 Register DstReg = I.getOperand(0).getReg(); in selectBallot() local
1181 const unsigned Size = MRI->getType(DstReg).getSizeInBits(); in selectBallot()
1194 BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg).addImm(0); in selectBallot()
1197 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(SrcReg); in selectBallot()
1202 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(SrcReg); in selectBallot()
1210 Register DstReg = I.getOperand(0).getReg(); in selectRelocConstant() local
1211 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectRelocConstant()
1213 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectRelocConstant()
1226 TII.get(IsVALU ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32), DstReg) in selectRelocConstant()
1236 Register DstReg = I.getOperand(0).getReg(); in selectGroupStaticSize() local
1237 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectGroupStaticSize()
1244 auto MIB = BuildMI(*MBB, &I, DL, TII.get(Mov), DstReg); in selectGroupStaticSize()
1266 Register DstReg = Dst.getReg(); in selectReturnAddress() local
1272 !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectReturnAddress()
1278 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_MOV_B64), DstReg) in selectReturnAddress()
1292 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), DstReg) in selectReturnAddress()
1361 Register DstReg = MI.getOperand(0).getReg(); in selectDSOrderedIntrinsic() local
1364 BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::DS_ORDERED_COUNT), DstReg) in selectDSOrderedIntrinsic()
1855 Register DstReg = I.getOperand(0).getReg(); in selectG_SELECT() local
1856 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_SELECT()
1871 MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg) in selectG_SELECT()
1887 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in selectG_SELECT()
1921 Register DstReg = I.getOperand(0).getReg(); in selectG_TRUNC() local
1923 const LLT DstTy = MRI->getType(DstReg); in selectG_TRUNC()
1934 DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_TRUNC()
1952 !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) { in selectG_TRUNC()
1972 BuildMI(*MBB, I, DL, TII.get(AMDGPU::V_MOV_B32_sdwa), DstReg) in selectG_TRUNC()
2004 BuildMI(*MBB, I, DL, TII.get(OrOpc), DstReg) in selectG_TRUNC()
2066 const Register DstReg = I.getOperand(0).getReg(); in selectG_SZA_EXT() local
2069 const LLT DstTy = MRI->getType(DstReg); in selectG_SZA_EXT()
2087 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_SZA_EXT()
2093 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg) in selectG_SZA_EXT()
2100 return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) && in selectG_SZA_EXT()
2111 BuildMI(MBB, I, DL, TII.get(AMDGPU::V_AND_B32_e32), DstReg) in selectG_SZA_EXT()
2120 BuildMI(MBB, I, DL, TII.get(BFE), DstReg) in selectG_SZA_EXT()
2137 BuildMI(MBB, I, DL, TII.get(SextOpc), DstReg) in selectG_SZA_EXT()
2140 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI); in selectG_SZA_EXT()
2160 BuildMI(MBB, I, DL, TII.get(BFE64), DstReg) in selectG_SZA_EXT()
2165 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, *MRI); in selectG_SZA_EXT()
2170 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_AND_B32), DstReg) in selectG_SZA_EXT()
2174 BuildMI(MBB, I, DL, TII.get(BFE32), DstReg) in selectG_SZA_EXT()
2180 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI); in selectG_SZA_EXT()
2189 Register DstReg = I.getOperand(0).getReg(); in selectG_CONSTANT() local
2190 unsigned Size = MRI->getType(DstReg).getSizeInBits(); in selectG_CONSTANT()
2202 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_CONSTANT()
2230 ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B64), DstReg) in selectG_CONSTANT()
2244 ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg) in selectG_CONSTANT()
2258 return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI); in selectG_CONSTANT()
2535 Register DstReg = I.getOperand(0).getReg(); in selectG_GLOBAL_VALUE() local
2536 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_GLOBAL_VALUE()
2543 DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI); in selectG_GLOBAL_VALUE()
2547 Register DstReg = I.getOperand(0).getReg(); in selectG_PTRMASK() local
2550 LLT Ty = MRI->getType(DstReg); in selectG_PTRMASK()
2555 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_PTRMASK()
2573 auto MIB = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_AND_B64), DstReg) in selectG_PTRMASK()
2589 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || in selectG_PTRMASK()
2598 BuildMI(*BB, &I, DL, TII.get(NewOpc), DstReg) in selectG_PTRMASK()
2645 BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg) in selectG_PTRMASK()
2684 Register DstReg = MI.getOperand(0).getReg(); in selectG_EXTRACT_VECTOR_ELT() local
2688 LLT DstTy = MRI->getType(DstReg); in selectG_EXTRACT_VECTOR_ELT()
2691 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_EXTRACT_VECTOR_ELT()
2707 !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || in selectG_EXTRACT_VECTOR_ELT()
2727 BuildMI(*BB, &MI, DL, TII.get(Opc), DstReg) in selectG_EXTRACT_VECTOR_ELT()
2740 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::V_MOVRELS_B32_e32), DstReg) in selectG_EXTRACT_VECTOR_ELT()
2749 BuildMI(*BB, MI, DL, GPRIDXDesc, DstReg) in selectG_EXTRACT_VECTOR_ELT()
2761 Register DstReg = MI.getOperand(0).getReg(); in selectG_INSERT_VECTOR_ELT() local
2766 LLT VecTy = MRI->getType(DstReg); in selectG_INSERT_VECTOR_ELT()
2788 !RBI.constrainGenericRegister(DstReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2812 BuildMI(*BB, MI, DL, RegWriteOp, DstReg) in selectG_INSERT_VECTOR_ELT()
2822 BuildMI(*BB, MI, DL, GPRIDXDesc, DstReg) in selectG_INSERT_VECTOR_ELT()
2865 Register DstReg = MI.getOperand(0).getReg(); in selectG_SHUFFLE_VECTOR() local
2871 if (MRI->getType(DstReg) != V2S16 || MRI->getType(Src0Reg) != V2S16) in selectG_SHUFFLE_VECTOR()
2882 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_SHUFFLE_VECTOR()
2889 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::IMPLICIT_DEF), DstReg); in selectG_SHUFFLE_VECTOR()
2892 return RBI.constrainGenericRegister(DstReg, RC, *MRI); in selectG_SHUFFLE_VECTOR()
2899 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI) || in selectG_SHUFFLE_VECTOR()
2905 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::COPY), DstReg) in selectG_SHUFFLE_VECTOR()
2914 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_LSHRREV_B32_e64), DstReg) in selectG_SHUFFLE_VECTOR()
2918 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_LSHR_B32), DstReg) in selectG_SHUFFLE_VECTOR()
2924 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_LSHLREV_B32_e64), DstReg) in selectG_SHUFFLE_VECTOR()
2928 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_LSHL_B32), DstReg) in selectG_SHUFFLE_VECTOR()
2937 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_MOV_B32_sdwa), DstReg) in selectG_SHUFFLE_VECTOR()
2951 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), DstReg) in selectG_SHUFFLE_VECTOR()
2957 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_PACK_LL_B32_B16), DstReg) in selectG_SHUFFLE_VECTOR()
2966 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_MOV_B32_sdwa), DstReg) in selectG_SHUFFLE_VECTOR()
2980 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), DstReg) in selectG_SHUFFLE_VECTOR()
2986 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_PACK_HH_B32_B16), DstReg) in selectG_SHUFFLE_VECTOR()
2992 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_ALIGNBIT_B32_e64), DstReg) in selectG_SHUFFLE_VECTOR()
2998 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_PACK_HL_B32_B16), DstReg) in selectG_SHUFFLE_VECTOR()
3006 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_PACK_LL_B32_B16), DstReg) in selectG_SHUFFLE_VECTOR()
3406 Register DstReg = MI.getOperand(0).getReg(); in selectWaveAddress() local
3408 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectWaveAddress()
3414 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_LSHRREV_B32_e64), DstReg) in selectWaveAddress()
3418 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_LSHR_B32), DstReg) in selectWaveAddress()
3425 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI)) in selectWaveAddress()