Lines Matching refs:DstReg
67 Register DstReg) { in buildMI() argument
68 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg); in buildMI()
161 Register DstReg = MI.getOperand(0).getReg(); in expandArith() local
168 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandArith()
194 Register DstReg = MI.getOperand(0).getReg(); in expandLogic() local
201 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogic()
242 Register DstReg = MI.getOperand(0).getReg(); in expandLogicImm() local
249 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogicImm()
296 Register DstReg = MI.getOperand(0).getReg(); in expand() local
300 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
350 Register DstReg = MI.getOperand(0).getReg(); in expand() local
359 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
415 Register DstReg = MI.getOperand(0).getReg(); in expand() local
421 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
447 Register DstReg = MI.getOperand(0).getReg(); in expand() local
451 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
485 Register DstReg = MI.getOperand(0).getReg(); in expand() local
493 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
518 Register DstReg = MI.getOperand(0).getReg(); in expand() local
526 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
553 Register DstReg = MI.getOperand(0).getReg(); in expand() local
557 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
604 Register DstReg = MI.getOperand(0).getReg(); in expand() local
608 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
650 Register DstReg = MI.getOperand(0).getReg(); in expand() local
656 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
659 if (DstReg == SrcReg) in expand()
662 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expand()
663 Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg; in expand()
699 Register DstReg = MI.getOperand(0).getReg(); in expand() local
705 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
707 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); in expand()
732 Register DstReg = MI.getOperand(0).getReg(); in expand() local
738 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
740 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); in expand()
765 Register DstReg = MI.getOperand(0).getReg(); in expand() local
772 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
779 if (DstReg == SrcReg) in expand()
782 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expand()
783 Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg; in expand()
819 Register DstReg = MI.getOperand(0).getReg(); in expandLPMWELPMW() local
825 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLPMWELPMW()
836 if (DstReg == SrcReg) in expandLPMWELPMW()
839 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expandLPMWELPMW()
840 Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg; in expandLPMWELPMW()
884 Register DstReg = MI.getOperand(0).getReg(); in expand() local
895 .addReg(DstReg, RegState::Define) in expand()
1063 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1073 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand()
1077 .addReg(DstReg, getUndefRegState(DstIsUndef)) in expand()
1092 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1101 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); in expand()
1104 .addReg(DstReg, RegState::Define) in expand()
1105 .addReg(DstReg, RegState::Kill) in expand()
1111 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1112 .addReg(DstReg, RegState::Kill) in expand()
1127 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1136 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); in expand()
1139 .addReg(DstReg, RegState::Define) in expand()
1140 .addReg(DstReg, RegState::Kill) in expand()
1146 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1147 .addReg(DstReg, RegState::Kill) in expand()
1162 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1172 buildMI(MBB, MBBI, AVR::PUSHWRr).addReg(DstReg); in expand()
1176 .addReg(DstReg, RegState::Define) in expand()
1177 .addReg(DstReg, RegState::Kill) in expand()
1181 .addReg(DstReg, RegState::Kill) in expand()
1185 buildMI(MBB, MBBI, AVR::POPWRd).addDef(DstReg, RegState::Define); in expand()
1194 .addReg(DstReg) in expand()
1199 .addReg(DstReg, getKillRegState(DstIsKill)) in expand()
1254 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1258 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1341 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1345 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1364 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1375 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1376 .addReg(DstReg, RegState::Kill) in expand()
1377 .addReg(DstReg, RegState::Kill); in expand()
1381 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1382 .addReg(DstReg, getKillRegState(DstIsKill)) in expand()
1401 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1408 buildMI(MBB, MBBI, AVR::BST).addReg(DstReg).addImm(0); in expand()
1411 buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg); in expand()
1414 buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7); in expand()
1424 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1430 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1458 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1462 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1481 Register DstReg = MI.getOperand(0).getReg(); in expandLSLW4Rd() local
1485 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSLW4Rd()
1539 Register DstReg = MI.getOperand(0).getReg(); in expandLSLW8Rd() local
1543 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSLW8Rd()
1566 Register DstReg = MI.getOperand(0).getReg(); in expandLSLW12Rd() local
1570 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSLW12Rd()
1625 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1631 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1657 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1661 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1679 Register DstReg = MI.getOperand(0).getReg(); in expandLSRW4Rd() local
1683 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSRW4Rd()
1737 Register DstReg = MI.getOperand(0).getReg(); in expandLSRW8Rd() local
1741 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSRW8Rd()
1764 Register DstReg = MI.getOperand(0).getReg(); in expandLSRW12Rd() local
1768 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSRW12Rd()
1835 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1841 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1867 Register DstReg = MI.getOperand(0).getReg(); in expand() local
1871 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1889 Register DstReg = MI.getOperand(0).getReg(); in expandASRW7Rd() local
1893 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandASRW7Rd()
1936 Register DstReg = MI.getOperand(0).getReg(); in expandASRW8Rd() local
1940 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandASRW8Rd()
1971 Register DstReg = MI.getOperand(0).getReg(); in expandASRW14Rd() local
1975 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandASRW14Rd()
2025 Register DstReg = MI.getOperand(0).getReg(); in expandASRW15Rd() local
2028 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandASRW15Rd()
2081 Register DstReg = MI.getOperand(0).getReg(); in expandLSLB7Rd() local
2091 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2092 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd()
2097 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2098 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd()
2099 .addReg(DstReg, RegState::Kill); in expandLSLB7Rd()
2103 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLB7Rd()
2104 .addReg(DstReg, getKillRegState(DstIsKill)); in expandLSLB7Rd()
2131 Register DstReg = MI.getOperand(0).getReg(); in expandLSRB7Rd() local
2141 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2142 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
2143 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
2148 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2149 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd()
2150 .addReg(DstReg, RegState::Kill); in expandLSRB7Rd()
2154 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRB7Rd()
2155 .addReg(DstReg, getKillRegState(DstIsKill)) in expandLSRB7Rd()
2156 .addReg(DstReg, getKillRegState(DstIsKill)); in expandLSRB7Rd()
2183 Register DstReg = MI.getOperand(0).getReg(); in expandASRB6Rd() local
2193 .addReg(DstReg) in expandASRB6Rd()
2199 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2200 .addReg(DstReg, RegState::Kill) in expandASRB6Rd()
2201 .addReg(DstReg, RegState::Kill); in expandASRB6Rd()
2204 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2205 .addReg(DstReg, RegState::Kill) in expandASRB6Rd()
2206 .addReg(DstReg, RegState::Kill); in expandASRB6Rd()
2209 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB6Rd()
2210 .addReg(DstReg, getKillRegState(DstIsKill)) in expandASRB6Rd()
2221 Register DstReg = MI.getOperand(0).getReg(); in expandASRB7Rd() local
2230 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB7Rd()
2231 .addReg(DstReg, RegState::Kill) in expandASRB7Rd()
2232 .addReg(DstReg, RegState::Kill); in expandASRB7Rd()
2236 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRB7Rd()
2237 .addReg(DstReg, getKillRegState(DstIsKill)) in expandASRB7Rd()
2238 .addReg(DstReg, getKillRegState(DstIsKill)); in expandASRB7Rd()
2281 Register DstReg = MI.getOperand(0).getReg(); in expand() local
2286 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
2333 Register DstReg = MI.getOperand(0).getReg(); in expand() local
2338 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
2363 Register DstReg = MI.getOperand(0).getReg(); in expand() local
2368 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()