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Searched refs:AMDGPU (Results 1 – 25 of 167) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp140 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
201 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass; in prepare()
443 return VGPR >= AMDGPU::VGPR0 && VGPR < AMDGPU::VGPR8; in isChainScratchRegister()
454 if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass) in getLargestLegalSuperClass()
456 if (RC == &AMDGPU::VReg_64RegClass || RC == &AMDGPU::AReg_64RegClass) in getLargestLegalSuperClass()
461 if (RC == &AMDGPU::VReg_96RegClass || RC == &AMDGPU::AReg_96RegClass) in getLargestLegalSuperClass()
466 if (RC == &AMDGPU::VReg_128RegClass || RC == &AMDGPU::AReg_128RegClass) in getLargestLegalSuperClass()
471 if (RC == &AMDGPU::VReg_160RegClass || RC == &AMDGPU::AReg_160RegClass) in getLargestLegalSuperClass()
2293 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr)) { in eliminateFrameIndex()
3118 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
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H A DAMDGPUCombinerHelper.cpp23 case AMDGPU::G_FADD: in fnegFoldsIntoMI()
24 case AMDGPU::G_FSUB: in fnegFoldsIntoMI()
25 case AMDGPU::G_FMUL: in fnegFoldsIntoMI()
26 case AMDGPU::G_FMA: in fnegFoldsIntoMI()
27 case AMDGPU::G_FMAD: in fnegFoldsIntoMI()
34 case AMDGPU::G_FSIN: in fnegFoldsIntoMI()
35 case AMDGPU::G_FPEXT: in fnegFoldsIntoMI()
38 case AMDGPU::G_FRINT: in fnegFoldsIntoMI()
83 case AMDGPU::COPY: in hasSourceMods()
85 case AMDGPU::G_FDIV: in hasSourceMods()
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H A DSIInstrInfo.cpp3254 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in insertSelect()
3255 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, in insertSelect()
3256 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, in insertSelect()
3257 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, in insertSelect()
3261 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3, in insertSelect()
3262 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7, in insertSelect()
3263 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11, in insertSelect()
3264 AMDGPU::sub12_sub13, AMDGPU::sub14_sub15, in insertSelect()
5218 case AMDGPU::COPY: return AMDGPU::COPY; in getVALUOp()
5219 case AMDGPU::PHI: return AMDGPU::PHI; in getVALUOp()
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H A DAMDGPUResourceUsageAnalysis.cpp39 using namespace llvm::AMDGPU;
115 if (AMDGPU::getAMDHSACodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5 || in runOnModule()
206 MRI.isPhysRegUsed(AMDGPU::VCC_LO) || MRI.isPhysRegUsed(AMDGPU::VCC_HI); in analyzeResourceUsage()
271 case AMDGPU::EXEC: in analyzeResourceUsage()
274 case AMDGPU::SCC: in analyzeResourceUsage()
275 case AMDGPU::M0: in analyzeResourceUsage()
288 case AMDGPU::MODE: in analyzeResourceUsage()
299 case AMDGPU::VCC: in analyzeResourceUsage()
300 case AMDGPU::VCC_LO: in analyzeResourceUsage()
322 case AMDGPU::TBA: in analyzeResourceUsage()
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H A DAMDGPURegisterBankInfo.cpp124 if (Opc == AMDGPU::G_ANYEXT || Opc == AMDGPU::G_ZEXT || in applyBank()
352 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsic()
355 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsic()
364 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
367 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
370 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
373 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
414 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
417 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsicWSideEffects()
792 AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term; in executeInWaterfallLoop()
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H A DSILoadStoreOptimizer.cpp425 !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr0)) in getInstClass()
537 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getInstSubclass()
645 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getRegs()
786 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr); in setMI()
789 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase); in setMI()
798 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr); in setMI()
1845 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, in getSubRegIdxs()
1846 {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4}, in getSubRegIdxs()
1847 {AMDGPU::sub2, AMDGPU::sub2_sub3, AMDGPU::sub2_sub3_sub4, AMDGPU::sub2_sub3_sub4_sub5}, in getSubRegIdxs()
1848 {AMDGPU::sub3, AMDGPU::sub3_sub4, AMDGPU::sub3_sub4_sub5, AMDGPU::sub3_sub4_sub5_sub6}, in getSubRegIdxs()
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H A DSIOptimizeExecMasking.cpp98 case AMDGPU::COPY: in isCopyFromExec()
99 case AMDGPU::S_MOV_B64: in isCopyFromExec()
101 case AMDGPU::S_MOV_B32: in isCopyFromExec()
115 case AMDGPU::COPY: in isCopyToExec()
136 case AMDGPU::S_OR_B64: in isLogicalOpOnExec()
152 case AMDGPU::S_OR_B32: in isLogicalOpOnExec()
176 case AMDGPU::S_OR_B64: in getSaveExecOp()
217 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
222 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
591 unsigned MovOpcode = IsSGPR32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in optimizeVCMPSaveExecSequence()
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H A DGCNDPPCombine.cpp180 case AMDGPU::COPY: in getOldOpndValue()
253 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old); in createDPPInst()
285 } else if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::src0_modifiers)) { in createDPPInst()
309 } else if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::src1_modifiers)) { in createDPPInst()
357 if (ClampOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::clamp)) { in createDPPInst()
362 AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::vdst_in)) { in createDPPInst()
366 if (OmodOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::omod)) { in createDPPInst()
385 if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::op_sel)) in createDPPInst()
403 if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::op_sel_hi)) in createDPPInst()
407 if (NegOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::neg_lo)) { in createDPPInst()
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H A DSIPeepholeSDWA.cpp989 SDWAOpcode = AMDGPU::getSDWAOp(AMDGPU::getVOPe32(Opcode)); in convertToSDWA()
1003 assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::vdst)); in convertToSDWA()
1006 assert(Dst && AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::sdst)); in convertToSDWA()
1009 assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::sdst)); in convertToSDWA()
1027 assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src1) && in convertToSDWA()
1047 assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::clamp)); in convertToSDWA()
1056 if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::omod)) { in convertToSDWA()
1066 if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::dst_sel)) { in convertToSDWA()
1076 if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::dst_unused)) { in convertToSDWA()
1086 assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src0_sel)); in convertToSDWA()
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H A DAMDGPUSubtarget.cpp232 case AMDGPU::V_RCP_F16_e64: in zeroesHigh16BitsOfDest()
233 case AMDGPU::V_RCP_F16_e32: in zeroesHigh16BitsOfDest()
234 case AMDGPU::V_RSQ_F16_e64: in zeroesHigh16BitsOfDest()
235 case AMDGPU::V_RSQ_F16_e32: in zeroesHigh16BitsOfDest()
238 case AMDGPU::V_LOG_F16_e64: in zeroesHigh16BitsOfDest()
239 case AMDGPU::V_LOG_F16_e32: in zeroesHigh16BitsOfDest()
303 case AMDGPU::V_MADAK_F16: in zeroesHigh16BitsOfDest()
304 case AMDGPU::V_MADMK_F16: in zeroesHigh16BitsOfDest()
307 case AMDGPU::V_FMAMK_F16: in zeroesHigh16BitsOfDest()
308 case AMDGPU::V_FMAAK_F16: in zeroesHigh16BitsOfDest()
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H A DAMDGPUInstructionSelector.cpp171 IsSGPR ? AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32; in selectCOPY()
286 return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32; in getLogicalBitOpcode()
288 return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32; in getLogicalBitOpcode()
290 return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32; in getLogicalBitOpcode()
446 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC) in selectG_UADDO_USUBO_UADDE_USUBE()
902 BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) in selectInterpP1F16()
1452 BuildCopy(IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC); in selectBallot()
1503 AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in selectGroupStaticSize()
2462 AMDGPU::SReg_64RegClass : AMDGPU::SReg_32RegClass; in selectG_SZA_EXT()
2468 AMDGPU::S_SEXT_I32_I8 : AMDGPU::S_SEXT_I32_I16; in selectG_SZA_EXT()
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H A DSIFoldOperands.cpp187 return OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in frameIndexMayFold()
191 int SIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr); in frameIndexMayFold()
195 int VIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in frameIndexMayFold()
250 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) { in tryFoldImmWithOpSel()
335 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::clamp); in tryFoldImmWithOpSel()
345 IsUAdd ? AMDGPU::V_PK_SUB_U16 : AMDGPU::V_PK_ADD_U16; in tryFoldImmWithOpSel()
604 if ((Opc == AMDGPU::S_FMAAK_F32 || Opc == AMDGPU::S_FMAMK_F32) && in tryAddToFoldList()
819 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr) && in foldOperand()
820 !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::saddr)) { in foldOperand()
984 AMDGPU::getNamedOperandIdx(UseOpc, AMDGPU::OpName::src0))) { in foldOperand()
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H A DSIShrinkInstructions.cpp94 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
237 if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) { in shrinkScalarCompare()
242 AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32; in shrinkScalarCompare()
264 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); in shrinkMIMG()
281 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in shrinkMIMG()
345 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in shrinkMIMG()
346 int LWEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::lwe); in shrinkMIMG()
377 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata), in shrinkMIMG()
766 Op->setReg(ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64); in tryReplaceDeadSDST()
780 unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
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H A DGCNHazardRecognizer.cpp99 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32; in isRWLane()
143 case AMDGPU::S_SENDMSG: in isSendMsgTraceDataOrGDS()
148 case AMDGPU::DS_NOP: in isSendMsgTraceDataOrGDS()
1123 Opc != AMDGPU::V_NOP_e64 && Opc != AMDGPU::V_NOP_sdwa; in fixVcmpxPermlaneHazards()
1212 const AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(ST.getCPU()); in fixSMEMtoVectorWriteHazards()
1247 AMDGPU::Waitcnt Decoded = AMDGPU::decodeWaitcnt(IV, Imm); in fixSMEMtoVectorWriteHazards()
1273 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL) in fixSMEMtoVectorWriteHazards()
1827 static_assert(AMDGPU::VGPR0 + 1 == AMDGPU::VGPR1); in fixShift64HighRegBug()
1912 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(I.getOpcode()); in checkNSAtoVMEMHazard()
2063 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in checkMAIHazards908()
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H A DAMDGPURemoveIncompatibleFunctions.cpp30 AMDGPUFeatureKV[AMDGPU::NumSubtargetFeatures - 1];
94 AMDGPU::FeatureGFX9Insts,
95 AMDGPU::FeatureGFX8Insts,
96 AMDGPU::FeatureDPP,
98 AMDGPU::FeatureDot1Insts,
99 AMDGPU::FeatureDot2Insts,
100 AMDGPU::FeatureDot3Insts,
101 AMDGPU::FeatureDot4Insts,
109 AMDGPU::FeatureGWS};
179 ST->hasFeature(AMDGPU::FeatureWavefrontSize32)) { in checkFunction()
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H A DAMDGPUArgumentUsageInfo.cpp100 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
104 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
107 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
110 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
113 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
117 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
120 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
124 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
128 &AMDGPU::SGPR_64RegClass, LLT::scalar(64)); in getPreloadedValue()
131 &AMDGPU::SGPR_64RegClass, LLT::scalar(64)); in getPreloadedValue()
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H A DSIInsertWaitcnts.cpp167 AMDGPU::S_WAIT_LOADCNT, AMDGPU::S_WAIT_DSCNT, AMDGPU::S_WAIT_EXPCNT,
168 AMDGPU::S_WAIT_STORECNT, AMDGPU::S_WAIT_SAMPLECNT, AMDGPU::S_WAIT_BVHCNT,
187 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode()); in getVmemType()
445 AMDGPU::IsaVersion IV;
1196 AMDGPU::Waitcnt OldWait = AMDGPU::decodeWaitcnt(IV, IEnc); in applyPreexistingWaitcnt()
1338 AMDGPU::Waitcnt OldWait = AMDGPU::decodeLoadcntDscnt(IV, OldEnc); in applyPreexistingWaitcnt()
1346 AMDGPU::Waitcnt OldWait = AMDGPU::decodeStorecntDscnt(IV, OldEnc); in applyPreexistingWaitcnt()
1728 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in generateWaitcntInstBefore()
2030 return Opc == AMDGPU::GLOBAL_INV || Opc == AMDGPU::GLOBAL_WB || in isCacheInvOrWBInst()
2105 if (Imm >= AMDGPU::Exp::ET_PARAM0 && Imm <= AMDGPU::Exp::ET_PARAM31) in updateEventWaitcntAfter()
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H A DSIPreAllocateWWMRegs.cpp168 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::ENTER_STRICT_WQM || in printWWMInfo()
169 Opc == AMDGPU::ENTER_PSEUDO_WM) { in printWWMInfo()
172 assert(Opc == AMDGPU::EXIT_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WQM || in printWWMInfo()
173 Opc == AMDGPU::EXIT_PSEUDO_WM); in printWWMInfo()
177 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WWM) { in printWWMInfo()
179 } else if (Opc == AMDGPU::ENTER_PSEUDO_WM || Opc == AMDGPU::EXIT_PSEUDO_WM) { in printWWMInfo()
182 assert(Opc == AMDGPU::ENTER_STRICT_WQM || Opc == AMDGPU::EXIT_STRICT_WQM); in printWWMInfo()
234 MI.getOpcode() == AMDGPU::ENTER_PSEUDO_WM) { in runOnMachineFunction()
240 if (MI.getOpcode() == AMDGPU::EXIT_STRICT_WWM || in runOnMachineFunction()
241 MI.getOpcode() == AMDGPU::EXIT_STRICT_WQM || in runOnMachineFunction()
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H A DSILateBranchLowering.cpp88 ? AMDGPU::Exp::ET_NULL in generateEndPgm()
89 : (HasColorExports ? AMDGPU::Exp::ET_MRT0 : AMDGPU::Exp::ET_MRTZ); in generateEndPgm()
92 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
129 MI.setDesc(TII->get(AMDGPU::SI_TCRETURN)); in expandChainCall()
154 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in runOnMachineFunction()
155 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
164 case AMDGPU::S_BRANCH: in runOnMachineFunction()
174 case AMDGPU::SI_CS_CHAIN_TC_W32: in runOnMachineFunction()
175 case AMDGPU::SI_CS_CHAIN_TC_W64: in runOnMachineFunction()
180 case AMDGPU::SI_EARLY_TERMINATE_SCC0: in runOnMachineFunction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp27 case AMDGPU::S_WAITCNT: in postProcessInstruction()
28 case AMDGPU::S_WAITCNT_soft: in postProcessInstruction()
29 case AMDGPU::S_WAITCNT_EXPCNT: in postProcessInstruction()
31 case AMDGPU::S_WAITCNT_VMCNT: in postProcessInstruction()
32 case AMDGPU::S_WAITCNT_VSCNT: in postProcessInstruction()
38 case AMDGPU::S_WAITCNT_gfx10: in postProcessInstruction()
40 case AMDGPU::S_WAITCNT_vi: in postProcessInstruction()
94 case AMDGPU::S_WAITCNT_vi: in checkCustomHazard()
180 AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(STI.getCPU()); in computeWaitCnt()
225 case AMDGPU::S_WAITCNT_vi: in computeWaitCnt()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp296 case AMDGPU::OPERAND_KIMM32: in getLitEncoding()
297 case AMDGPU::OPERAND_KIMM16: in getLitEncoding()
381 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm)) in encodeInstruction()
448 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()
458 if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { in getSDWASrcEncoding()
478 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()
485 if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) { in getSDWAVopcDstEncoding()
582 SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in getMachineOpValueT16()
584 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst); in getMachineOpValueT16()
592 SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1); in getMachineOpValueT16()
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H A DAMDGPUInstPrinter.cpp326 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); in printSymbolicFormat()
366 case AMDGPU::FP_REG: in printRegOperand()
367 case AMDGPU::SP_REG: in printRegOperand()
370 case AMDGPU::SCC: in printRegOperand()
443 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
1182 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
1185 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); in printExpSrcN()
1264 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0}, in printPackedModifier()
1265 {AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1}, in printPackedModifier()
1266 {AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}}; in printPackedModifier()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2549 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { in AddNextRegisterToList()
2564 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { in AddNextRegisterToList()
2569 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { in AddNextRegisterToList()
2574 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { in AddNextRegisterToList()
3744 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGAddrSize()
3851 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGMSAA()
4748 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) { in validateCoherencyBits()
8238 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::high)) in cvtVOP3Interp()
8246 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod)) in cvtVOP3Interp()
8338 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod)) in cvtVOP3()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp365 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; in IsAGPROperand()
937 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); in isMacDPP()
981 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { in convertDPP8Inst()
1017 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { in convertVOP3DPPInst()
1185 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) in convertVOP3PDPPInst()
1189 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) in convertVOP3PDPPInst()
1193 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) in convertVOP3PDPPInst()
1197 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) in convertVOP3PDPPInst()
1201 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) in convertVOP3PDPPInst()
1214 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) in convertVOPCDPPInst()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp158 namespace AMDGPU { namespace
495 return AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0X); in isVOPD()
1205 if (AMDGPU::isGFX90A(*STI)) { in getDefaultAmdhsaKernelDescriptor()
2265 Reg == AMDGPU::SCC; in isSGPR()
2273 using namespace AMDGPU; \
2361 case AMDGPU::SRC_VCCZ: in isInlineValue()
2362 case AMDGPU::SRC_EXECZ: in isInlineValue()
2363 case AMDGPU::SRC_SCC: in isInlineValue()
2365 case AMDGPU::SGPR_NULL: in isInlineValue()
2868 if (AMDGPU::isGFX10(ST)) in getNumFlatOffsetBits()
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