Lines Matching refs:AMDGPU
167 AddrOp->getReg() != AMDGPU::SGPR_NULL) in hasMergeableAddress()
323 return AMDGPU::getMUBUFElements(Opc); in getOpcodeWidth()
327 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
331 return AMDGPU::getMTBUFElements(Opc); in getOpcodeWidth()
335 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getOpcodeWidth()
336 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM: in getOpcodeWidth()
337 case AMDGPU::S_LOAD_DWORD_IMM: in getOpcodeWidth()
338 case AMDGPU::GLOBAL_LOAD_DWORD: in getOpcodeWidth()
339 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getOpcodeWidth()
340 case AMDGPU::GLOBAL_STORE_DWORD: in getOpcodeWidth()
341 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getOpcodeWidth()
342 case AMDGPU::FLAT_LOAD_DWORD: in getOpcodeWidth()
343 case AMDGPU::FLAT_STORE_DWORD: in getOpcodeWidth()
345 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getOpcodeWidth()
346 case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM: in getOpcodeWidth()
347 case AMDGPU::S_LOAD_DWORDX2_IMM: in getOpcodeWidth()
348 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getOpcodeWidth()
349 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getOpcodeWidth()
350 case AMDGPU::GLOBAL_STORE_DWORDX2: in getOpcodeWidth()
351 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getOpcodeWidth()
352 case AMDGPU::FLAT_LOAD_DWORDX2: in getOpcodeWidth()
353 case AMDGPU::FLAT_STORE_DWORDX2: in getOpcodeWidth()
355 case AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM: in getOpcodeWidth()
356 case AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM: in getOpcodeWidth()
357 case AMDGPU::S_LOAD_DWORDX3_IMM: in getOpcodeWidth()
358 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getOpcodeWidth()
359 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getOpcodeWidth()
360 case AMDGPU::GLOBAL_STORE_DWORDX3: in getOpcodeWidth()
361 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getOpcodeWidth()
362 case AMDGPU::FLAT_LOAD_DWORDX3: in getOpcodeWidth()
363 case AMDGPU::FLAT_STORE_DWORDX3: in getOpcodeWidth()
365 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getOpcodeWidth()
366 case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM: in getOpcodeWidth()
367 case AMDGPU::S_LOAD_DWORDX4_IMM: in getOpcodeWidth()
368 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getOpcodeWidth()
369 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getOpcodeWidth()
370 case AMDGPU::GLOBAL_STORE_DWORDX4: in getOpcodeWidth()
371 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getOpcodeWidth()
372 case AMDGPU::FLAT_LOAD_DWORDX4: in getOpcodeWidth()
373 case AMDGPU::FLAT_STORE_DWORDX4: in getOpcodeWidth()
375 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getOpcodeWidth()
376 case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM: in getOpcodeWidth()
377 case AMDGPU::S_LOAD_DWORDX8_IMM: in getOpcodeWidth()
379 case AMDGPU::DS_READ_B32: [[fallthrough]]; in getOpcodeWidth()
380 case AMDGPU::DS_READ_B32_gfx9: [[fallthrough]]; in getOpcodeWidth()
381 case AMDGPU::DS_WRITE_B32: [[fallthrough]]; in getOpcodeWidth()
382 case AMDGPU::DS_WRITE_B32_gfx9: in getOpcodeWidth()
384 case AMDGPU::DS_READ_B64: [[fallthrough]]; in getOpcodeWidth()
385 case AMDGPU::DS_READ_B64_gfx9: [[fallthrough]]; in getOpcodeWidth()
386 case AMDGPU::DS_WRITE_B64: [[fallthrough]]; in getOpcodeWidth()
387 case AMDGPU::DS_WRITE_B64_gfx9: in getOpcodeWidth()
399 switch (AMDGPU::getMUBUFBaseOpcode(Opc)) { in getInstClass()
402 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN: in getInstClass()
403 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_exact: in getInstClass()
404 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET: in getInstClass()
405 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_exact: in getInstClass()
406 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN: in getInstClass()
407 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN_exact: in getInstClass()
408 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET: in getInstClass()
409 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET_exact: in getInstClass()
411 case AMDGPU::BUFFER_STORE_DWORD_OFFEN: in getInstClass()
412 case AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact: in getInstClass()
413 case AMDGPU::BUFFER_STORE_DWORD_OFFSET: in getInstClass()
414 case AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact: in getInstClass()
415 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN: in getInstClass()
416 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact: in getInstClass()
417 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET: in getInstClass()
418 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact: in getInstClass()
424 if (!AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr) && in getInstClass()
425 !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr0)) in getInstClass()
428 if (AMDGPU::getMIMGBaseOpcode(Opc)->BVH) in getInstClass()
437 switch (AMDGPU::getMTBUFBaseOpcode(Opc)) { in getInstClass()
440 case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN: in getInstClass()
441 case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_exact: in getInstClass()
442 case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN: in getInstClass()
443 case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_exact: in getInstClass()
444 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN: in getInstClass()
445 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_exact: in getInstClass()
446 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET: in getInstClass()
447 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_exact: in getInstClass()
448 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN: in getInstClass()
449 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_exact: in getInstClass()
450 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN: in getInstClass()
451 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_exact: in getInstClass()
452 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN: in getInstClass()
453 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_exact: in getInstClass()
454 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET: in getInstClass()
455 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_exact: in getInstClass()
457 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN: in getInstClass()
458 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_exact: in getInstClass()
459 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET: in getInstClass()
460 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_exact: in getInstClass()
461 case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN: in getInstClass()
462 case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact: in getInstClass()
463 case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET: in getInstClass()
464 case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact: in getInstClass()
469 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getInstClass()
470 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getInstClass()
471 case AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM: in getInstClass()
472 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getInstClass()
473 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getInstClass()
475 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM: in getInstClass()
476 case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM: in getInstClass()
477 case AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM: in getInstClass()
478 case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM: in getInstClass()
479 case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM: in getInstClass()
481 case AMDGPU::S_LOAD_DWORD_IMM: in getInstClass()
482 case AMDGPU::S_LOAD_DWORDX2_IMM: in getInstClass()
483 case AMDGPU::S_LOAD_DWORDX3_IMM: in getInstClass()
484 case AMDGPU::S_LOAD_DWORDX4_IMM: in getInstClass()
485 case AMDGPU::S_LOAD_DWORDX8_IMM: in getInstClass()
487 case AMDGPU::DS_READ_B32: in getInstClass()
488 case AMDGPU::DS_READ_B32_gfx9: in getInstClass()
489 case AMDGPU::DS_READ_B64: in getInstClass()
490 case AMDGPU::DS_READ_B64_gfx9: in getInstClass()
492 case AMDGPU::DS_WRITE_B32: in getInstClass()
493 case AMDGPU::DS_WRITE_B32_gfx9: in getInstClass()
494 case AMDGPU::DS_WRITE_B64: in getInstClass()
495 case AMDGPU::DS_WRITE_B64_gfx9: in getInstClass()
497 case AMDGPU::GLOBAL_LOAD_DWORD: in getInstClass()
498 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getInstClass()
499 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getInstClass()
500 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getInstClass()
501 case AMDGPU::FLAT_LOAD_DWORD: in getInstClass()
502 case AMDGPU::FLAT_LOAD_DWORDX2: in getInstClass()
503 case AMDGPU::FLAT_LOAD_DWORDX3: in getInstClass()
504 case AMDGPU::FLAT_LOAD_DWORDX4: in getInstClass()
506 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getInstClass()
507 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getInstClass()
508 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getInstClass()
509 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getInstClass()
511 case AMDGPU::GLOBAL_STORE_DWORD: in getInstClass()
512 case AMDGPU::GLOBAL_STORE_DWORDX2: in getInstClass()
513 case AMDGPU::GLOBAL_STORE_DWORDX3: in getInstClass()
514 case AMDGPU::GLOBAL_STORE_DWORDX4: in getInstClass()
515 case AMDGPU::FLAT_STORE_DWORD: in getInstClass()
516 case AMDGPU::FLAT_STORE_DWORDX2: in getInstClass()
517 case AMDGPU::FLAT_STORE_DWORDX3: in getInstClass()
518 case AMDGPU::FLAT_STORE_DWORDX4: in getInstClass()
520 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getInstClass()
521 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getInstClass()
522 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getInstClass()
523 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getInstClass()
535 return AMDGPU::getMUBUFBaseOpcode(Opc); in getInstSubclass()
537 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getInstSubclass()
542 return AMDGPU::getMTBUFBaseOpcode(Opc); in getInstSubclass()
544 case AMDGPU::DS_READ_B32: in getInstSubclass()
545 case AMDGPU::DS_READ_B32_gfx9: in getInstSubclass()
546 case AMDGPU::DS_READ_B64: in getInstSubclass()
547 case AMDGPU::DS_READ_B64_gfx9: in getInstSubclass()
548 case AMDGPU::DS_WRITE_B32: in getInstSubclass()
549 case AMDGPU::DS_WRITE_B32_gfx9: in getInstSubclass()
550 case AMDGPU::DS_WRITE_B64: in getInstSubclass()
551 case AMDGPU::DS_WRITE_B64_gfx9: in getInstSubclass()
553 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getInstSubclass()
554 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getInstSubclass()
555 case AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM: in getInstSubclass()
556 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getInstSubclass()
557 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getInstSubclass()
558 return AMDGPU::S_BUFFER_LOAD_DWORD_IMM; in getInstSubclass()
559 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM: in getInstSubclass()
560 case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM: in getInstSubclass()
561 case AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM: in getInstSubclass()
562 case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM: in getInstSubclass()
563 case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM: in getInstSubclass()
564 return AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM; in getInstSubclass()
565 case AMDGPU::S_LOAD_DWORD_IMM: in getInstSubclass()
566 case AMDGPU::S_LOAD_DWORDX2_IMM: in getInstSubclass()
567 case AMDGPU::S_LOAD_DWORDX3_IMM: in getInstSubclass()
568 case AMDGPU::S_LOAD_DWORDX4_IMM: in getInstSubclass()
569 case AMDGPU::S_LOAD_DWORDX8_IMM: in getInstSubclass()
570 return AMDGPU::S_LOAD_DWORD_IMM; in getInstSubclass()
571 case AMDGPU::GLOBAL_LOAD_DWORD: in getInstSubclass()
572 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getInstSubclass()
573 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getInstSubclass()
574 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getInstSubclass()
575 case AMDGPU::FLAT_LOAD_DWORD: in getInstSubclass()
576 case AMDGPU::FLAT_LOAD_DWORDX2: in getInstSubclass()
577 case AMDGPU::FLAT_LOAD_DWORDX3: in getInstSubclass()
578 case AMDGPU::FLAT_LOAD_DWORDX4: in getInstSubclass()
579 return AMDGPU::FLAT_LOAD_DWORD; in getInstSubclass()
580 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getInstSubclass()
581 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getInstSubclass()
582 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getInstSubclass()
583 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getInstSubclass()
584 return AMDGPU::GLOBAL_LOAD_DWORD_SADDR; in getInstSubclass()
585 case AMDGPU::GLOBAL_STORE_DWORD: in getInstSubclass()
586 case AMDGPU::GLOBAL_STORE_DWORDX2: in getInstSubclass()
587 case AMDGPU::GLOBAL_STORE_DWORDX3: in getInstSubclass()
588 case AMDGPU::GLOBAL_STORE_DWORDX4: in getInstSubclass()
589 case AMDGPU::FLAT_STORE_DWORD: in getInstSubclass()
590 case AMDGPU::FLAT_STORE_DWORDX2: in getInstSubclass()
591 case AMDGPU::FLAT_STORE_DWORDX3: in getInstSubclass()
592 case AMDGPU::FLAT_STORE_DWORDX4: in getInstSubclass()
593 return AMDGPU::FLAT_STORE_DWORD; in getInstSubclass()
594 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getInstSubclass()
595 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getInstSubclass()
596 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getInstSubclass()
597 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getInstSubclass()
598 return AMDGPU::GLOBAL_STORE_DWORD_SADDR; in getInstSubclass()
624 if (AMDGPU::getMUBUFHasVAddr(Opc)) in getRegs()
626 if (AMDGPU::getMUBUFHasSrsrc(Opc)) in getRegs()
628 if (AMDGPU::getMUBUFHasSoffset(Opc)) in getRegs()
635 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs()
638 TII.isMIMG(Opc) ? AMDGPU::OpName::srsrc : AMDGPU::OpName::rsrc; in getRegs()
639 int RsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RsrcName); in getRegs()
645 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getRegs()
646 if (Info && AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode)->Sampler) in getRegs()
652 if (AMDGPU::getMTBUFHasVAddr(Opc)) in getRegs()
654 if (AMDGPU::getMTBUFHasSrsrc(Opc)) in getRegs()
656 if (AMDGPU::getMTBUFHasSoffset(Opc)) in getRegs()
665 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM: in getRegs()
666 case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM: in getRegs()
667 case AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM: in getRegs()
668 case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM: in getRegs()
669 case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM: in getRegs()
672 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getRegs()
673 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getRegs()
674 case AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM: in getRegs()
675 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getRegs()
676 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getRegs()
677 case AMDGPU::S_LOAD_DWORD_IMM: in getRegs()
678 case AMDGPU::S_LOAD_DWORDX2_IMM: in getRegs()
679 case AMDGPU::S_LOAD_DWORDX3_IMM: in getRegs()
680 case AMDGPU::S_LOAD_DWORDX4_IMM: in getRegs()
681 case AMDGPU::S_LOAD_DWORDX8_IMM: in getRegs()
684 case AMDGPU::DS_READ_B32: in getRegs()
685 case AMDGPU::DS_READ_B64: in getRegs()
686 case AMDGPU::DS_READ_B32_gfx9: in getRegs()
687 case AMDGPU::DS_READ_B64_gfx9: in getRegs()
688 case AMDGPU::DS_WRITE_B32: in getRegs()
689 case AMDGPU::DS_WRITE_B64: in getRegs()
690 case AMDGPU::DS_WRITE_B32_gfx9: in getRegs()
691 case AMDGPU::DS_WRITE_B64_gfx9: in getRegs()
694 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getRegs()
695 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getRegs()
696 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getRegs()
697 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getRegs()
698 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getRegs()
699 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getRegs()
700 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getRegs()
701 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getRegs()
704 case AMDGPU::GLOBAL_LOAD_DWORD: in getRegs()
705 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getRegs()
706 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getRegs()
707 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getRegs()
708 case AMDGPU::GLOBAL_STORE_DWORD: in getRegs()
709 case AMDGPU::GLOBAL_STORE_DWORDX2: in getRegs()
710 case AMDGPU::GLOBAL_STORE_DWORDX3: in getRegs()
711 case AMDGPU::GLOBAL_STORE_DWORDX4: in getRegs()
712 case AMDGPU::FLAT_LOAD_DWORD: in getRegs()
713 case AMDGPU::FLAT_LOAD_DWORDX2: in getRegs()
714 case AMDGPU::FLAT_LOAD_DWORDX3: in getRegs()
715 case AMDGPU::FLAT_LOAD_DWORDX4: in getRegs()
716 case AMDGPU::FLAT_STORE_DWORD: in getRegs()
717 case AMDGPU::FLAT_STORE_DWORDX2: in getRegs()
718 case AMDGPU::FLAT_STORE_DWORDX3: in getRegs()
719 case AMDGPU::FLAT_STORE_DWORDX4: in getRegs()
739 (Opc == AMDGPU::DS_READ_B64 || Opc == AMDGPU::DS_READ_B64_gfx9) ? 8 in setMI()
744 (Opc == AMDGPU::DS_WRITE_B64 || Opc == AMDGPU::DS_WRITE_B64_gfx9) ? 8 in setMI()
750 EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4); in setMI()
758 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
762 int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset); in setMI()
767 Format = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
774 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
783 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) + J; in setMI()
786 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr); in setMI()
789 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase); in setMI()
791 AddrIdx[NumAddresses++] = AMDGPU::getNamedOperandIdx( in setMI()
792 Opc, isVIMAGEorVSAMPLE ? AMDGPU::OpName::rsrc : AMDGPU::OpName::srsrc); in setMI()
795 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset); in setMI()
798 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr); in setMI()
801 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in setMI()
803 AddrIdx[NumAddresses++] = AMDGPU::getNamedOperandIdx( in setMI()
804 Opc, isVIMAGEorVSAMPLE ? AMDGPU::OpName::samp : AMDGPU::OpName::ssamp); in setMI()
887 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
888 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
894 unsigned OperandsToMatch[] = {AMDGPU::OpName::cpol, AMDGPU::OpName::d16, in dmasksCanBeCombined()
895 AMDGPU::OpName::unorm, AMDGPU::OpName::da, in dmasksCanBeCombined()
896 AMDGPU::OpName::r128, AMDGPU::OpName::a16}; in dmasksCanBeCombined()
899 int Idx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), op); in dmasksCanBeCombined()
900 if (AMDGPU::getNamedOperandIdx(Paired.I->getOpcode(), op) != Idx) in dmasksCanBeCombined()
927 const llvm::AMDGPU::GcnBufferFormatInfo *OldFormatInfo = in getBufferFormatWithCompCount()
928 llvm::AMDGPU::getGcnBufferFormatInfo(OldFormat, STI); in getBufferFormatWithCompCount()
932 const llvm::AMDGPU::GcnBufferFormatInfo *NewFormatInfo = in getBufferFormatWithCompCount()
933 llvm::AMDGPU::getGcnBufferFormatInfo(OldFormatInfo->BitsPerComp, in getBufferFormatWithCompCount()
973 const llvm::AMDGPU::GcnBufferFormatInfo *Info0 = in offsetsCanBeCombined()
974 llvm::AMDGPU::getGcnBufferFormatInfo(CI.Format, STI); in offsetsCanBeCombined()
977 const llvm::AMDGPU::GcnBufferFormatInfo *Info1 = in offsetsCanBeCombined()
978 llvm::AMDGPU::getGcnBufferFormatInfo(Paired.Format, STI); in offsetsCanBeCombined()
1105 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
1108 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) { in getDataRegClass()
1111 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
1114 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
1117 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::sdata)) { in getDataRegClass()
1180 return (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64; in read2Opcode()
1181 return (EltSize == 4) ? AMDGPU::DS_READ2_B32_gfx9 : AMDGPU::DS_READ2_B64_gfx9; in read2Opcode()
1186 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64; in read2ST64Opcode()
1188 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32_gfx9 in read2ST64Opcode()
1189 : AMDGPU::DS_READ2ST64_B64_gfx9; in read2ST64Opcode()
1199 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair()
1201 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1202 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1209 unsigned SubRegIdx0 = (CI.EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1; in mergeRead2Pair()
1210 unsigned SubRegIdx1 = (CI.EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3; in mergeRead2Pair()
1232 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeRead2Pair()
1233 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
1236 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeRead2Pair()
1275 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64; in write2Opcode()
1276 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32_gfx9 in write2Opcode()
1277 : AMDGPU::DS_WRITE2_B64_gfx9; in write2Opcode()
1282 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 in write2ST64Opcode()
1283 : AMDGPU::DS_WRITE2ST64_B64; in write2ST64Opcode()
1285 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32_gfx9 in write2ST64Opcode()
1286 : AMDGPU::DS_WRITE2ST64_B64_gfx9; in write2ST64Opcode()
1297 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeWrite2Pair()
1299 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1301 TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1324 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeWrite2Pair()
1325 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
1328 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeWrite2Pair()
1367 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask); in mergeImagePair()
1389 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeImagePair()
1390 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeImagePair()
1423 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)); in mergeSMemLoadImmPair()
1425 New.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)); in mergeSMemLoadImmPair()
1435 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSMemLoadImmPair()
1436 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::sdst); in mergeSMemLoadImmPair()
1469 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferLoadPair()
1477 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferLoadPair()
1478 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
1490 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1491 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1524 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferLoadPair()
1535 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferLoadPair()
1536 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferLoadPair()
1549 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1550 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1580 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1581 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1583 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeTBufferStorePair()
1595 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferStorePair()
1606 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferStorePair()
1607 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferStorePair()
1632 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr)) in mergeFlatLoadPair()
1636 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)) in mergeFlatLoadPair()
1647 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeFlatLoadPair()
1648 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdst); in mergeFlatLoadPair()
1678 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeFlatStorePair()
1679 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeFlatStorePair()
1681 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeFlatStorePair()
1688 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)) in mergeFlatStorePair()
1691 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr)) in mergeFlatStorePair()
1712 return AMDGPU::getMUBUFOpcode(AMDGPU::getMUBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1716 return AMDGPU::getMTBUFOpcode(AMDGPU::getMTBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1726 return AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM; in getNewOpcode()
1728 return AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM; in getNewOpcode()
1730 return AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM; in getNewOpcode()
1732 return AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM; in getNewOpcode()
1739 return AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM; in getNewOpcode()
1741 return AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM; in getNewOpcode()
1743 return AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM; in getNewOpcode()
1745 return AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM; in getNewOpcode()
1752 return AMDGPU::S_LOAD_DWORDX2_IMM; in getNewOpcode()
1754 return AMDGPU::S_LOAD_DWORDX3_IMM; in getNewOpcode()
1756 return AMDGPU::S_LOAD_DWORDX4_IMM; in getNewOpcode()
1758 return AMDGPU::S_LOAD_DWORDX8_IMM; in getNewOpcode()
1765 return AMDGPU::GLOBAL_LOAD_DWORDX2; in getNewOpcode()
1767 return AMDGPU::GLOBAL_LOAD_DWORDX3; in getNewOpcode()
1769 return AMDGPU::GLOBAL_LOAD_DWORDX4; in getNewOpcode()
1776 return AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR; in getNewOpcode()
1778 return AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR; in getNewOpcode()
1780 return AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR; in getNewOpcode()
1787 return AMDGPU::GLOBAL_STORE_DWORDX2; in getNewOpcode()
1789 return AMDGPU::GLOBAL_STORE_DWORDX3; in getNewOpcode()
1791 return AMDGPU::GLOBAL_STORE_DWORDX4; in getNewOpcode()
1798 return AMDGPU::GLOBAL_STORE_DWORDX2_SADDR; in getNewOpcode()
1800 return AMDGPU::GLOBAL_STORE_DWORDX3_SADDR; in getNewOpcode()
1802 return AMDGPU::GLOBAL_STORE_DWORDX4_SADDR; in getNewOpcode()
1809 return AMDGPU::FLAT_LOAD_DWORDX2; in getNewOpcode()
1811 return AMDGPU::FLAT_LOAD_DWORDX3; in getNewOpcode()
1813 return AMDGPU::FLAT_LOAD_DWORDX4; in getNewOpcode()
1820 return AMDGPU::FLAT_STORE_DWORDX2; in getNewOpcode()
1822 return AMDGPU::FLAT_STORE_DWORDX3; in getNewOpcode()
1824 return AMDGPU::FLAT_STORE_DWORDX4; in getNewOpcode()
1829 return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width); in getNewOpcode()
1845 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, in getSubRegIdxs()
1846 {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4}, in getSubRegIdxs()
1847 {AMDGPU::sub2, AMDGPU::sub2_sub3, AMDGPU::sub2_sub3_sub4, AMDGPU::sub2_sub3_sub4_sub5}, in getSubRegIdxs()
1848 {AMDGPU::sub3, AMDGPU::sub3_sub4, AMDGPU::sub3_sub4_sub5, AMDGPU::sub3_sub4_sub5_sub6}, in getSubRegIdxs()
1849 {AMDGPU::sub4, AMDGPU::sub4_sub5, AMDGPU::sub4_sub5_sub6, AMDGPU::sub4_sub5_sub6_sub7}, in getSubRegIdxs()
1875 return &AMDGPU::SReg_64_XEXECRegClass; in getTargetRegisterClass()
1877 return &AMDGPU::SGPR_96RegClass; in getTargetRegisterClass()
1879 return &AMDGPU::SGPR_128RegClass; in getTargetRegisterClass()
1881 return &AMDGPU::SGPR_256RegClass; in getTargetRegisterClass()
1883 return &AMDGPU::SGPR_512RegClass; in getTargetRegisterClass()
1909 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1910 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1912 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeBufferStorePair()
1924 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferStorePair()
1933 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferStorePair()
1934 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
1951 Register Reg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in createRegOrImm()
1954 TII->get(AMDGPU::S_MOV_B32), Reg) in createRegOrImm()
1981 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in computeBase()
1985 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1986 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1988 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0) in computeBase()
1997 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
2010 .addImm(AMDGPU::sub0) in computeBase()
2012 .addImm(AMDGPU::sub1); in computeBase()
2023 auto Base = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in updateBaseAndOffset()
2026 TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset); in updateBaseAndOffset()
2038 if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 || in extractConstOffset()
2061 if (!Def || Def->getOpcode() != AMDGPU::REG_SEQUENCE in processBaseWithConstOffset()
2073 if (!BaseLoDef || BaseLoDef->getOpcode() != AMDGPU::V_ADD_CO_U32_e64 || in processBaseWithConstOffset()
2074 !BaseHiDef || BaseHiDef->getOpcode() != AMDGPU::V_ADDC_U32_e64) in processBaseWithConstOffset()
2077 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
2078 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
2089 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
2090 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
2117 if (AMDGPU::getGlobalSaddrOp(MI.getOpcode()) < 0) in promoteConstantOffsetToImm()
2121 TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != nullptr) in promoteConstantOffsetToImm()
2129 if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) { in promoteConstantOffsetToImm()
2135 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
2194 TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm()) in promoteConstantOffsetToImm()
2198 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
2307 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); in collectMergeableInsts()