Lines Matching refs:AMDGPU
94 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
153 if (AMDGPU::VGPR_32RegClass.contains(Reg) && in shouldShrinkTrue16()
154 !AMDGPU::VGPR_32_Lo128RegClass.contains(Reg)) in shouldShrinkTrue16()
231 int SOPKOpc = AMDGPU::getSOPKOp(MI.getOpcode()); in shrinkScalarCompare()
237 if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) { in shrinkScalarCompare()
241 SOPKOpc = (SOPKOpc == AMDGPU::S_CMPK_EQ_U32) ? in shrinkScalarCompare()
242 AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32; in shrinkScalarCompare()
264 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); in shrinkMIMG()
270 case AMDGPU::MIMGEncGfx10NSA: in shrinkMIMG()
271 NewEncoding = AMDGPU::MIMGEncGfx10Default; in shrinkMIMG()
273 case AMDGPU::MIMGEncGfx11NSA: in shrinkMIMG()
274 NewEncoding = AMDGPU::MIMGEncGfx11Default; in shrinkMIMG()
281 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in shrinkMIMG()
286 RC = &AMDGPU::VReg_64RegClass; in shrinkMIMG()
288 RC = &AMDGPU::VReg_96RegClass; in shrinkMIMG()
290 RC = &AMDGPU::VReg_128RegClass; in shrinkMIMG()
292 RC = &AMDGPU::VReg_160RegClass; in shrinkMIMG()
294 RC = &AMDGPU::VReg_192RegClass; in shrinkMIMG()
296 RC = &AMDGPU::VReg_224RegClass; in shrinkMIMG()
298 RC = &AMDGPU::VReg_256RegClass; in shrinkMIMG()
300 RC = &AMDGPU::VReg_288RegClass; in shrinkMIMG()
302 RC = &AMDGPU::VReg_320RegClass; in shrinkMIMG()
304 RC = &AMDGPU::VReg_352RegClass; in shrinkMIMG()
306 RC = &AMDGPU::VReg_384RegClass; in shrinkMIMG()
308 RC = &AMDGPU::VReg_512RegClass; in shrinkMIMG()
345 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in shrinkMIMG()
346 int LWEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::lwe); in shrinkMIMG()
365 unsigned NewOpcode = AMDGPU::getMIMGOpcode(Info->BaseOpcode, NewEncoding, in shrinkMIMG()
377 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata), in shrinkMIMG()
398 MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0); in shrinkMadFma()
399 MachineOperand &Src1 = *TII->getNamedOperand(MI, AMDGPU::OpName::src1); in shrinkMadFma()
400 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); in shrinkMadFma()
401 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END; in shrinkMadFma()
417 case AMDGPU::V_MAD_F32_e64: in shrinkMadFma()
418 NewOpcode = AMDGPU::V_MADAK_F32; in shrinkMadFma()
420 case AMDGPU::V_FMA_F32_e64: in shrinkMadFma()
421 NewOpcode = AMDGPU::V_FMAAK_F32; in shrinkMadFma()
423 case AMDGPU::V_MAD_F16_e64: in shrinkMadFma()
424 NewOpcode = AMDGPU::V_MADAK_F16; in shrinkMadFma()
426 case AMDGPU::V_FMA_F16_e64: in shrinkMadFma()
427 case AMDGPU::V_FMA_F16_gfx9_e64: in shrinkMadFma()
428 NewOpcode = ST->hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_t16 in shrinkMadFma()
429 : AMDGPU::V_FMAAK_F16; in shrinkMadFma()
446 case AMDGPU::V_MAD_F32_e64: in shrinkMadFma()
447 NewOpcode = AMDGPU::V_MADMK_F32; in shrinkMadFma()
449 case AMDGPU::V_FMA_F32_e64: in shrinkMadFma()
450 NewOpcode = AMDGPU::V_FMAMK_F32; in shrinkMadFma()
452 case AMDGPU::V_MAD_F16_e64: in shrinkMadFma()
453 NewOpcode = AMDGPU::V_MADMK_F16; in shrinkMadFma()
455 case AMDGPU::V_FMA_F16_e64: in shrinkMadFma()
456 case AMDGPU::V_FMA_F16_gfx9_e64: in shrinkMadFma()
457 NewOpcode = ST->hasTrue16BitInsts() ? AMDGPU::V_FMAMK_F16_t16 in shrinkMadFma()
458 : AMDGPU::V_FMAMK_F16; in shrinkMadFma()
463 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) in shrinkMadFma()
466 if (AMDGPU::isTrue16Inst(NewOpcode) && !shouldShrinkTrue16(MI)) in shrinkMadFma()
498 AMDGPU::isInlinableLiteral32(SrcImm->getImm(), ST->hasInv2PiInlineImm())) in shrinkScalarLogicOp()
504 if (Opc == AMDGPU::S_AND_B32) { in shrinkScalarLogicOp()
507 Opc = AMDGPU::S_BITSET0_B32; in shrinkScalarLogicOp()
508 } else if (AMDGPU::isInlinableLiteral32(~Imm, ST->hasInv2PiInlineImm())) { in shrinkScalarLogicOp()
510 Opc = AMDGPU::S_ANDN2_B32; in shrinkScalarLogicOp()
512 } else if (Opc == AMDGPU::S_OR_B32) { in shrinkScalarLogicOp()
515 Opc = AMDGPU::S_BITSET1_B32; in shrinkScalarLogicOp()
516 } else if (AMDGPU::isInlinableLiteral32(~Imm, ST->hasInv2PiInlineImm())) { in shrinkScalarLogicOp()
518 Opc = AMDGPU::S_ORN2_B32; in shrinkScalarLogicOp()
520 } else if (Opc == AMDGPU::S_XOR_B32) { in shrinkScalarLogicOp()
521 if (AMDGPU::isInlinableLiteral32(~Imm, ST->hasInv2PiInlineImm())) { in shrinkScalarLogicOp()
523 Opc = AMDGPU::S_XNOR_B32; in shrinkScalarLogicOp()
540 if (Opc == AMDGPU::S_BITSET0_B32 || in shrinkScalarLogicOp()
541 Opc == AMDGPU::S_BITSET1_B32) { in shrinkScalarLogicOp()
613 TII->get(AMDGPU::IMPLICIT_DEF), Op.getReg()); in dropInstructionKeepingImpDefs()
639 assert(MovT.getOpcode() == AMDGPU::V_MOV_B32_e32 || in matchSwap()
640 MovT.getOpcode() == AMDGPU::COPY); in matchSwap()
666 if ((MovY->getOpcode() != AMDGPU::V_MOV_B32_e32 && in matchSwap()
667 MovY->getOpcode() != AMDGPU::COPY) || in matchSwap()
696 (I->getOpcode() != AMDGPU::V_MOV_B32_e32 && in matchSwap()
697 I->getOpcode() != AMDGPU::COPY) || in matchSwap()
721 TII->get(AMDGPU::V_SWAP_B32)) in matchSwap()
726 if (MovX->hasRegisterImplicitUseOperand(AMDGPU::EXEC)) { in matchSwap()
759 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in tryReplaceDeadSDST()
766 Op->setReg(ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64); in tryReplaceDeadSDST()
780 unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
793 if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) { in runOnMachineFunction()
806 MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32)); in runOnMachineFunction()
813 if (ST->hasSwap() && (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 || in runOnMachineFunction()
814 MI.getOpcode() == AMDGPU::COPY)) { in runOnMachineFunction()
822 if (MI.getOpcode() == AMDGPU::S_ADD_I32 || in runOnMachineFunction()
823 MI.getOpcode() == AMDGPU::S_MUL_I32) { in runOnMachineFunction()
844 unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ? in runOnMachineFunction()
845 AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32; in runOnMachineFunction()
861 if (MI.getOpcode() == AMDGPU::S_MOV_B32) { in runOnMachineFunction()
868 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); in runOnMachineFunction()
871 MI.setDesc(TII->get(AMDGPU::S_BREV_B32)); in runOnMachineFunction()
880 if (MI.getOpcode() == AMDGPU::S_AND_B32 || in runOnMachineFunction()
881 MI.getOpcode() == AMDGPU::S_OR_B32 || in runOnMachineFunction()
882 MI.getOpcode() == AMDGPU::S_XOR_B32) { in runOnMachineFunction()
898 if (MI.getOpcode() == AMDGPU::V_MAD_F32_e64 || in runOnMachineFunction()
899 MI.getOpcode() == AMDGPU::V_FMA_F32_e64 || in runOnMachineFunction()
900 MI.getOpcode() == AMDGPU::V_MAD_F16_e64 || in runOnMachineFunction()
901 MI.getOpcode() == AMDGPU::V_FMA_F16_e64 || in runOnMachineFunction()
902 MI.getOpcode() == AMDGPU::V_FMA_F16_gfx9_e64) { in runOnMachineFunction()
924 int Op32 = AMDGPU::getVOPe32(MI.getOpcode()); in runOnMachineFunction()
950 if (Op32 == AMDGPU::V_CNDMASK_B32_e32) { in runOnMachineFunction()
954 TII->getNamedOperand(MI, AMDGPU::OpName::src2); in runOnMachineFunction()
968 AMDGPU::OpName::sdst); in runOnMachineFunction()
982 AMDGPU::OpName::src2); in runOnMachineFunction()
1002 if (ST->hasTrue16BitInsts() && AMDGPU::isTrue16Inst(MI.getOpcode()) && in runOnMachineFunction()