154       STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))  in getLit16Encoding()
190       STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))  in getLit32Encoding()
226       STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))  in getLit64Encoding()
254   case AMDGPU::OPERAND_REG_IMM_INT32:  in getLitEncoding()
255   case AMDGPU::OPERAND_REG_IMM_FP32:  in getLitEncoding()
256   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:  in getLitEncoding()
257   case AMDGPU::OPERAND_REG_INLINE_C_INT32:  in getLitEncoding()
258   case AMDGPU::OPERAND_REG_INLINE_C_FP32:  in getLitEncoding()
259   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:  in getLitEncoding()
260   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:  in getLitEncoding()
261   case AMDGPU::OPERAND_REG_IMM_V2INT32:  in getLitEncoding()
262   case AMDGPU::OPERAND_REG_IMM_V2FP32:  in getLitEncoding()
263   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:  in getLitEncoding()
264   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:  in getLitEncoding()
265   case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:  in getLitEncoding()
268   case AMDGPU::OPERAND_REG_IMM_INT64:  in getLitEncoding()
269   case AMDGPU::OPERAND_REG_IMM_FP64:  in getLitEncoding()
270   case AMDGPU::OPERAND_REG_INLINE_C_INT64:  in getLitEncoding()
271   case AMDGPU::OPERAND_REG_INLINE_C_FP64:  in getLitEncoding()
272   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:  in getLitEncoding()
275   case AMDGPU::OPERAND_REG_IMM_INT16:  in getLitEncoding()
276   case AMDGPU::OPERAND_REG_INLINE_C_INT16:  in getLitEncoding()
277   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:  in getLitEncoding()
279   case AMDGPU::OPERAND_REG_IMM_FP16:  in getLitEncoding()
280   case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:  in getLitEncoding()
281   case AMDGPU::OPERAND_REG_INLINE_C_FP16:  in getLitEncoding()
282   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:  in getLitEncoding()
286   case AMDGPU::OPERAND_REG_IMM_V2INT16:  in getLitEncoding()
287   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:  in getLitEncoding()
288   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:  in getLitEncoding()
289     return AMDGPU::getInlineEncodingV2I16(static_cast<uint32_t>(Imm))  in getLitEncoding()
291   case AMDGPU::OPERAND_REG_IMM_V2FP16:  in getLitEncoding()
292   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:  in getLitEncoding()
293   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:  in getLitEncoding()
294     return AMDGPU::getInlineEncodingV2F16(static_cast<uint32_t>(Imm))  in getLitEncoding()
296   case AMDGPU::OPERAND_KIMM32:  in getLitEncoding()
297   case AMDGPU::OPERAND_KIMM16:  in getLitEncoding()
305   using namespace AMDGPU::VOP3PEncoding;  in getImplicitOpSelHiEncoding()
306   using namespace AMDGPU::OpName;  in getImplicitOpSelHiEncoding()
308   if (AMDGPU::hasNamedOperand(Opcode, op_sel_hi)) {  in getImplicitOpSelHiEncoding()
309     if (AMDGPU::hasNamedOperand(Opcode, src2))  in getImplicitOpSelHiEncoding()
311     if (AMDGPU::hasNamedOperand(Opcode, src1))  in getImplicitOpSelHiEncoding()
313     if (AMDGPU::hasNamedOperand(Opcode, src0))  in getImplicitOpSelHiEncoding()
321          Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC);  in isVCMPX64()
337       Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||  in encodeInstruction()
338       Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) {  in encodeInstruction()
348   if (AMDGPU::isGFX10Plus(STI) && isVCMPX64(Desc)) {  in encodeInstruction()
350     Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO) &  in encodeInstruction()
351                 AMDGPU::HWEncoding::REG_IDX_MASK;  in encodeInstruction()
359   if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {  in encodeInstruction()
360     int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in encodeInstruction()
361                                             AMDGPU::OpName::vaddr0);  in encodeInstruction()
362     int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in encodeInstruction()
363                                            AMDGPU::OpName::srsrc);  in encodeInstruction()
376   if ((bytes > 8 && STI.hasFeature(AMDGPU::FeatureVOP3Literal)) ||  in encodeInstruction()
377       (bytes > 4 && !STI.hasFeature(AMDGPU::FeatureVOP3Literal)))  in encodeInstruction()
381   if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm))  in encodeInstruction()
388     if (!AMDGPU::isSISrcOperand(Desc, i))  in encodeInstruction()
409     if (Desc.operands()[i].OperandType == AMDGPU::OPERAND_REG_IMM_FP64)  in encodeInstruction()
427     MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;  in getSOPPBrEncoding()
440   assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));  in getSMEMOffsetEncoding()
448   using namespace AMDGPU::SDWA;  in getSDWASrcEncoding()
458     if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {  in getSDWASrcEncoding()
478   using namespace AMDGPU::SDWA;  in getSDWAVopcDstEncoding()
485   if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {  in getSDWAVopcDstEncoding()
498   unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;  in getAVOperandEncoding()
499   bool IsVGPROrAGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;  in getAVOperandEncoding()
505   if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||  in getAVOperandEncoding()
506       MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||  in getAVOperandEncoding()
507       MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||  in getAVOperandEncoding()
508       MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||  in getAVOperandEncoding()
509       MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||  in getAVOperandEncoding()
510       MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||  in getAVOperandEncoding()
511       MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) ||  in getAVOperandEncoding()
512       MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||  in getAVOperandEncoding()
513       MRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) ||  in getAVOperandEncoding()
514       MRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) ||  in getAVOperandEncoding()
515       MRI.getRegClass(AMDGPU::AReg_352RegClassID).contains(Reg) ||  in getAVOperandEncoding()
516       MRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) ||  in getAVOperandEncoding()
517       MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) ||  in getAVOperandEncoding()
518       MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))  in getAVOperandEncoding()
553     unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;  in getMachineOpValue()
554     bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;  in getMachineOpValue()
568     unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;  in getMachineOpValueT16()
569     bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;  in getMachineOpValueT16()
580   if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in getMachineOpValueT16()
581                                               AMDGPU::OpName::src0_modifiers)) {  in getMachineOpValueT16()
582     SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);  in getMachineOpValueT16()
584         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst);  in getMachineOpValueT16()
587       if (AMDGPU::isHi(DstReg, MRI))  in getMachineOpValueT16()
590   } else if ((int)OpNo == AMDGPU::getNamedOperandIdx(  in getMachineOpValueT16()
591                               MI.getOpcode(), AMDGPU::OpName::src1_modifiers))  in getMachineOpValueT16()
592     SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1);  in getMachineOpValueT16()
593   else if ((int)OpNo == AMDGPU::getNamedOperandIdx(  in getMachineOpValueT16()
594                             MI.getOpcode(), AMDGPU::OpName::src2_modifiers))  in getMachineOpValueT16()
595     SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src2);  in getMachineOpValueT16()
603   if (AMDGPU::isSGPR(SrcReg, &MRI))  in getMachineOpValueT16()
605   if (AMDGPU::isHi(SrcReg, MRI))  in getMachineOpValueT16()
615     unsigned RegIdx = Encoding & AMDGPU::HWEncoding::REG_IDX_MASK;  in getMachineOpValueT16Lo128()
616     bool IsHi = Encoding & AMDGPU::HWEncoding::IS_HI;  in getMachineOpValueT16Lo128()
617     bool IsVGPR = Encoding & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;  in getMachineOpValueT16Lo128()
654   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {  in getMachineOpValueCommon()