Lines Matching refs:AMDGPU
62 MaxLookAhead = MF.getRegInfo().isPhysRegUsed(AMDGPU::AGPR0) ? 19 : 5; in GCNHazardRecognizer()
80 return Opcode == AMDGPU::V_DIV_FMAS_F32_e64 || Opcode == AMDGPU::V_DIV_FMAS_F64_e64; in isDivFMas()
84 return Opcode == AMDGPU::S_GETREG_B32; in isSGetReg()
89 case AMDGPU::S_SETREG_B32: in isSSetReg()
90 case AMDGPU::S_SETREG_B32_mode: in isSSetReg()
91 case AMDGPU::S_SETREG_IMM32_B32: in isSSetReg()
92 case AMDGPU::S_SETREG_IMM32_B32_mode: in isSSetReg()
99 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32; in isRWLane()
103 return Opcode == AMDGPU::S_RFE_B64; in isRFE()
108 case AMDGPU::S_MOVRELS_B32: in isSMovRel()
109 case AMDGPU::S_MOVRELS_B64: in isSMovRel()
110 case AMDGPU::S_MOVRELD_B32: in isSMovRel()
111 case AMDGPU::S_MOVRELD_B64: in isSMovRel()
119 return AMDGPU::getMAIIsDGEMM(Opcode); in isDGEMM()
127 Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_e64 || in isXDL()
128 Opcode == AMDGPU::V_ACCVGPR_READ_B32_e64) in isXDL()
134 return AMDGPU::getMAIIsGFX940XDL(Opcode); in isXDL()
143 case AMDGPU::S_SENDMSG: in isSendMsgTraceDataOrGDS()
144 case AMDGPU::S_SENDMSGHALT: in isSendMsgTraceDataOrGDS()
145 case AMDGPU::S_TTRACEDATA: in isSendMsgTraceDataOrGDS()
148 case AMDGPU::DS_NOP: in isSendMsgTraceDataOrGDS()
149 case AMDGPU::DS_PERMUTE_B32: in isSendMsgTraceDataOrGDS()
150 case AMDGPU::DS_BPERMUTE_B32: in isSendMsgTraceDataOrGDS()
154 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in isSendMsgTraceDataOrGDS()
155 AMDGPU::OpName::gds); in isSendMsgTraceDataOrGDS()
165 return Opcode == AMDGPU::V_PERMLANE16_B32_e64 || in isPermlane()
166 Opcode == AMDGPU::V_PERMLANE64_B32 || in isPermlane()
167 Opcode == AMDGPU::V_PERMLANEX16_B32_e64 || in isPermlane()
168 Opcode == AMDGPU::V_PERMLANE16_VAR_B32_e64 || in isPermlane()
169 Opcode == AMDGPU::V_PERMLANEX16_VAR_B32_e64; in isPermlane()
179 AMDGPU::OpName::simm16); in getHWReg()
180 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_; in getHWReg()
239 MI->getOpcode() == AMDGPU::DS_WRITE_ADDTID_B32 || in getHazardType()
240 MI->getOpcode() == AMDGPU::DS_READ_ADDTID_B32)) || in getHazardType()
244 MI->readsRegister(AMDGPU::LDS_DIRECT))) && in getHazardType()
267 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP)) in insertNoopsInBundle()
380 MI->getOpcode() == AMDGPU::DS_WRITE_ADDTID_B32 || in PreEmitNoopsCommon()
381 MI->getOpcode() == AMDGPU::DS_READ_ADDTID_B32)) || in PreEmitNoopsCommon()
384 (ST.hasReadM0LdsDirectHazard() && MI->readsRegister(AMDGPU::LDS_DIRECT))) in PreEmitNoopsCommon()
764 DppExecWaitStates - getWaitStatesSinceDef(AMDGPU::EXEC, IsHazardDefFn, in checkDPPHazards()
779 int WaitStatesNeeded = getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn, in checkDivFMasHazards()
818 int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); in createsVALUHazard()
831 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
834 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 && in createsVALUHazard()
844 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc); in createsVALUHazard()
846 AMDGPU::getRegBitWidth(Desc.operands()[SRsrcIdx].RegClass) == 256); in createsVALUHazard()
851 int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); in createsVALUHazard()
852 if (AMDGPU::getRegBitWidth(Desc.operands()[DataIdx].RegClass) > 64) in createsVALUHazard()
895 Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg(); in checkVALUHazards()
919 if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel)) in checkVALUHazards()
920 if (DstSel->getImm() == AMDGPU::SDWA::DWORD) in checkVALUHazards()
923 if (!AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::op_sel) || in checkVALUHazards()
924 !(TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers) in checkVALUHazards()
930 if (auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in checkVALUHazards()
976 if (VALU->readsRegister(AMDGPU::VCC, TRI)) { in checkVALUHazards()
977 UseReg = AMDGPU::VCC; in checkVALUHazards()
985 case AMDGPU::V_READLANE_B32: in checkVALUHazards()
986 case AMDGPU::V_READFIRSTLANE_B32: { in checkVALUHazards()
987 MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0); in checkVALUHazards()
995 case AMDGPU::V_WRITELANE_B32: { in checkVALUHazards()
996 UseReg = AMDGPU::EXEC; in checkVALUHazards()
1054 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); in checkRWLaneHazards()
1077 return getHWReg(TII, MI) == AMDGPU::Hwreg::ID_TRAPSTS; in checkRFEHazards()
1088 getWaitStatesSinceDef(AMDGPU::M0, IsHazardFn, ReadM0WaitStates); in checkReadM0Hazards()
1117 MI.modifiesRegister(AMDGPU::EXEC, TRI); in fixVcmpxPermlaneHazards()
1122 return SIInstrInfo::isVALU(MI) && Opc != AMDGPU::V_NOP_e32 && in fixVcmpxPermlaneHazards()
1123 Opc != AMDGPU::V_NOP_e64 && Opc != AMDGPU::V_NOP_sdwa; in fixVcmpxPermlaneHazards()
1133 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in fixVcmpxPermlaneHazards()
1137 TII->get(AMDGPU::V_MOV_B32_e32)) in fixVcmpxPermlaneHazards()
1174 (MI.getOpcode() == AMDGPU::S_WAITCNT && in fixVMEMtoScalarWriteHazards()
1176 (MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && in fixVMEMtoScalarWriteHazards()
1177 AMDGPU::DepCtr::decodeFieldVmVsrc(MI.getOperand(0).getImm()) == 0); in fixVMEMtoScalarWriteHazards()
1186 TII->get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVMEMtoScalarWriteHazards()
1187 .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0)); in fixVMEMtoScalarWriteHazards()
1201 case AMDGPU::V_READLANE_B32: in fixSMEMtoVectorWriteHazards()
1202 case AMDGPU::V_READFIRSTLANE_B32: in fixSMEMtoVectorWriteHazards()
1203 SDSTName = AMDGPU::OpName::vdst; in fixSMEMtoVectorWriteHazards()
1206 SDSTName = AMDGPU::OpName::sdst; in fixSMEMtoVectorWriteHazards()
1212 const AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(ST.getCPU()); in fixSMEMtoVectorWriteHazards()
1234 case AMDGPU::S_SETVSKIP: in fixSMEMtoVectorWriteHazards()
1235 case AMDGPU::S_VERSION: in fixSMEMtoVectorWriteHazards()
1236 case AMDGPU::S_WAITCNT_VSCNT: in fixSMEMtoVectorWriteHazards()
1237 case AMDGPU::S_WAITCNT_VMCNT: in fixSMEMtoVectorWriteHazards()
1238 case AMDGPU::S_WAITCNT_EXPCNT: in fixSMEMtoVectorWriteHazards()
1241 case AMDGPU::S_WAITCNT_LGKMCNT: in fixSMEMtoVectorWriteHazards()
1244 (MI.getOperand(0).getReg() == AMDGPU::SGPR_NULL); in fixSMEMtoVectorWriteHazards()
1245 case AMDGPU::S_WAITCNT: { in fixSMEMtoVectorWriteHazards()
1247 AMDGPU::Waitcnt Decoded = AMDGPU::decodeWaitcnt(IV, Imm); in fixSMEMtoVectorWriteHazards()
1273 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL) in fixSMEMtoVectorWriteHazards()
1287 if (!MI->modifiesRegister(AMDGPU::EXEC, TRI)) in fixVcmpxExecWARHazard()
1293 return I.readsRegister(AMDGPU::EXEC, TRI); in fixVcmpxExecWARHazard()
1299 if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) in fixVcmpxExecWARHazard()
1305 if (MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && in fixVcmpxExecWARHazard()
1306 AMDGPU::DepCtr::decodeFieldSaSdst(MI.getOperand(0).getImm()) == 0) in fixVcmpxExecWARHazard()
1316 TII->get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVcmpxExecWARHazard()
1317 .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0)); in fixVcmpxExecWARHazard()
1343 return I.getOpcode() == AMDGPU::S_WAITCNT_VSCNT && in isStoreCountWaitZero()
1344 I.getOperand(0).getReg() == AMDGPU::SGPR_NULL && in isStoreCountWaitZero()
1398 TII->get(AMDGPU::S_WAITCNT_VSCNT)) in fixLdsBranchVmemWARHazard()
1399 .addReg(AMDGPU::SGPR_NULL, RegState::Undef) in fixLdsBranchVmemWARHazard()
1410 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVALUHazard()
1443 TII.getNamedOperand(*MI, AMDGPU::OpName::waitvdst); in fixLdsDirectVALUHazard()
1453 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVMEMHazard()
1467 (I.getOpcode() == AMDGPU::S_WAITCNT && !I.getOperand(0).getImm()) || in fixLdsDirectVMEMHazard()
1468 (I.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && in fixLdsDirectVMEMHazard()
1469 AMDGPU::DepCtr::decodeFieldVmVsrc(I.getOperand(0).getImm()) == 0) || in fixLdsDirectVMEMHazard()
1471 !TII.getNamedOperand(I, AMDGPU::OpName::waitvsrc)->getImm()); in fixLdsDirectVMEMHazard()
1479 TII.getNamedOperand(*MI, AMDGPU::OpName::waitvsrc)->setImm(0); in fixLdsDirectVMEMHazard()
1482 TII.get(AMDGPU::S_WAITCNT_DEPCTR)) in fixLdsDirectVMEMHazard()
1483 .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0)); in fixLdsDirectVMEMHazard()
1545 (I.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && in fixVALUPartialForwardingHazard()
1546 AMDGPU::DepCtr::decodeFieldVaVdst(I.getOperand(0).getImm()) == 0)) in fixVALUPartialForwardingHazard()
1560 if (!State.DefPos.empty() && I.modifiesRegister(AMDGPU::EXEC, &TRI)) { in fixVALUPartialForwardingHazard()
1632 TII.get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVALUPartialForwardingHazard()
1682 (I.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && in fixVALUTransUseHazard()
1712 TII.get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVALUTransUseHazard()
1713 .addImm(AMDGPU::DepCtr::encodeFieldVaVdst(0)); in fixVALUTransUseHazard()
1732 TII->getNamedOperand(*MI, AMDGPU::OpName::src0)->getReg(); in fixWMMAHazards()
1734 TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg(); in fixWMMAHazards()
1737 TII->getNamedOperand(I, AMDGPU::OpName::vdst)->getReg(); in fixWMMAHazards()
1747 TII->getNamedOperand(*MI, AMDGPU::OpName::src2); in fixWMMAHazards()
1750 if (CurSrc2Reg != AMDGPU::NoRegister && in fixWMMAHazards()
1754 TII->getNamedOperand(*MI, AMDGPU::OpName::src2_modifiers); in fixWMMAHazards()
1766 if (AMDGPU::isGFX12Plus(ST)) { in fixWMMAHazards()
1769 TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->getReg(); in fixWMMAHazards()
1787 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::V_NOP_e32)); in fixWMMAHazards()
1800 case AMDGPU::V_LSHLREV_B64_e64: in fixShift64HighRegBug()
1801 case AMDGPU::V_LSHRREV_B64_e64: in fixShift64HighRegBug()
1802 case AMDGPU::V_ASHRREV_I64_e64: in fixShift64HighRegBug()
1806 MachineOperand *Amt = TII.getNamedOperand(*MI, AMDGPU::OpName::src0); in fixShift64HighRegBug()
1813 if (!TRI.isVGPR(MRI, AmtReg) || ((AmtReg - AMDGPU::VGPR0) & 7) != 7) in fixShift64HighRegBug()
1816 if (AmtReg != AMDGPU::VGPR255 && MRI.isPhysRegUsed(AmtReg + 1)) in fixShift64HighRegBug()
1819 MachineOperand *Src1 = TII.getNamedOperand(*MI, AMDGPU::OpName::src1); in fixShift64HighRegBug()
1827 static_assert(AMDGPU::VGPR0 + 1 == AMDGPU::VGPR1); in fixShift64HighRegBug()
1830 for (MCRegister Reg : Overlapped ? AMDGPU::VReg_64_Align2RegClass in fixShift64HighRegBug()
1831 : AMDGPU::VGPR_32RegClass) { in fixShift64HighRegBug()
1838 Register NewAmt = Overlapped ? (Register)TRI.getSubReg(NewReg, AMDGPU::sub1) in fixShift64HighRegBug()
1843 NewAmtLo = TRI.getSubReg(NewReg, AMDGPU::sub0); in fixShift64HighRegBug()
1848 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_WAITCNT)) in fixShift64HighRegBug()
1854 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_SWAP_B32), NewAmtLo) in fixShift64HighRegBug()
1858 runOnInstruction(BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_SWAP_B32), NewAmt) in fixShift64HighRegBug()
1865 BuildMI(*MBB, std::next(MI->getIterator()), DL, TII.get(AMDGPU::V_SWAP_B32), in fixShift64HighRegBug()
1871 BuildMI(*MBB, std::next(MI->getIterator()), DL, TII.get(AMDGPU::V_SWAP_B32), in fixShift64HighRegBug()
1905 const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset); in checkNSAtoVMEMHazard()
1912 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(I.getOpcode()); in checkNSAtoVMEMHazard()
1913 return Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA && in checkNSAtoVMEMHazard()
1927 if (MI->getOpcode() != AMDGPU::S_DENORM_MODE) in checkFPAtomicToDenormModeHazard()
1941 case AMDGPU::S_WAITCNT: in checkFPAtomicToDenormModeHazard()
1942 case AMDGPU::S_WAITCNT_VSCNT: in checkFPAtomicToDenormModeHazard()
1943 case AMDGPU::S_WAITCNT_VMCNT: in checkFPAtomicToDenormModeHazard()
1944 case AMDGPU::S_WAITCNT_EXPCNT: in checkFPAtomicToDenormModeHazard()
1945 case AMDGPU::S_WAITCNT_LGKMCNT: in checkFPAtomicToDenormModeHazard()
1946 case AMDGPU::S_WAIT_IDLE: in checkFPAtomicToDenormModeHazard()
2003 if (Opc != AMDGPU::V_ACCVGPR_READ_B32_e64) { // MFMA or v_accvgpr_write in checkMAIHazards908()
2009 getWaitStatesSinceDef(AMDGPU::EXEC, IsVALUFn, MaxWaitStates); in checkMAIHazards908()
2033 if (Op.isDef() && Opc != AMDGPU::V_ACCVGPR_WRITE_B32_e64) in checkMAIHazards908()
2063 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in checkMAIHazards908()
2067 } else if (Opc == AMDGPU::V_ACCVGPR_READ_B32_e64) { in checkMAIHazards908()
2077 } else if (Opc == AMDGPU::V_ACCVGPR_WRITE_B32_e64) { in checkMAIHazards908()
2096 if (MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64) in checkMAIHazards908()
2108 else if (Opc == AMDGPU::V_ACCVGPR_READ_B32_e64) in checkMAIHazards908()
2119 if (Opc == AMDGPU::V_ACCVGPR_WRITE_B32_e64) { in checkMAIHazards908()
2131 Register Reg = TII.getNamedOperand(MI, AMDGPU::OpName::src2)->getReg(); in checkMAIHazards908()
2177 getWaitStatesSinceDef(AMDGPU::EXEC, IsLegacyVALUFn, in checkMAIHazards90A()
2181 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in checkMAIHazards90A()
2250 if ((Opc == AMDGPU::V_MFMA_F64_4X4X4F64_e64 || in checkMAIHazards90A()
2251 Opc == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64) && in checkMAIHazards90A()
2252 (Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_e64 || in checkMAIHazards90A()
2253 Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64)) in checkMAIHazards90A()
2260 case AMDGPU::V_MFMA_F64_16X16X4F64_e64: in checkMAIHazards90A()
2261 case AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64: in checkMAIHazards90A()
2262 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64: in checkMAIHazards90A()
2263 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64: in checkMAIHazards90A()
2267 case AMDGPU::V_MFMA_F64_4X4X4F64_e64: in checkMAIHazards90A()
2268 case AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64: in checkMAIHazards90A()
2314 case AMDGPU::V_MFMA_F64_16X16X4F64_e64: in checkMAIHazards90A()
2315 case AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64: in checkMAIHazards90A()
2316 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64: in checkMAIHazards90A()
2317 case AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64: in checkMAIHazards90A()
2320 case AMDGPU::V_MFMA_F64_4X4X4F64_e64: in checkMAIHazards90A()
2321 case AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64: in checkMAIHazards90A()
2377 return MI.getOpcode() == AMDGPU::V_ACCVGPR_READ_B32_e64; in checkMAILdStHazards()
2398 if (MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64 && in checkMAILdStHazards()
2399 MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64) in checkMAILdStHazards()
2471 int SrcCIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), in checkMAIVALUHazards()
2472 AMDGPU::OpName::src2); in checkMAIVALUHazards()
2591 if ((Opc == AMDGPU::V_FMA_F64_e64 || in checkMAIVALUHazards()
2592 Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64 || in checkMAIVALUHazards()
2593 Opc == AMDGPU::V_FMAC_F64_dpp) && in checkMAIVALUHazards()
2690 TII.getNamedOperand(MI, AMDGPU::OpName::src2); in checkMAIVALUHazards()
2766 const MachineOperand *SDSTOp = TII.getNamedOperand(*MI, AMDGPU::OpName::sdst); in fixVALUMaskWriteHazard()
2771 if (HazardReg == AMDGPU::EXEC || in fixVALUMaskWriteHazard()
2772 HazardReg == AMDGPU::EXEC_LO || in fixVALUMaskWriteHazard()
2773 HazardReg == AMDGPU::EXEC_HI || in fixVALUMaskWriteHazard()
2774 HazardReg == AMDGPU::M0) in fixVALUMaskWriteHazard()
2779 case AMDGPU::V_ADDC_U32_e32: in fixVALUMaskWriteHazard()
2780 case AMDGPU::V_ADDC_U32_dpp: in fixVALUMaskWriteHazard()
2781 case AMDGPU::V_CNDMASK_B16_e32: in fixVALUMaskWriteHazard()
2782 case AMDGPU::V_CNDMASK_B16_dpp: in fixVALUMaskWriteHazard()
2783 case AMDGPU::V_CNDMASK_B32_e32: in fixVALUMaskWriteHazard()
2784 case AMDGPU::V_CNDMASK_B32_dpp: in fixVALUMaskWriteHazard()
2785 case AMDGPU::V_DIV_FMAS_F32_e64: in fixVALUMaskWriteHazard()
2786 case AMDGPU::V_DIV_FMAS_F64_e64: in fixVALUMaskWriteHazard()
2787 case AMDGPU::V_SUBB_U32_e32: in fixVALUMaskWriteHazard()
2788 case AMDGPU::V_SUBB_U32_dpp: in fixVALUMaskWriteHazard()
2789 case AMDGPU::V_SUBBREV_U32_e32: in fixVALUMaskWriteHazard()
2790 case AMDGPU::V_SUBBREV_U32_dpp: in fixVALUMaskWriteHazard()
2792 return HazardReg == AMDGPU::VCC || in fixVALUMaskWriteHazard()
2793 HazardReg == AMDGPU::VCC_LO || in fixVALUMaskWriteHazard()
2794 HazardReg == AMDGPU::VCC_HI; in fixVALUMaskWriteHazard()
2795 case AMDGPU::V_ADDC_U32_e64: in fixVALUMaskWriteHazard()
2796 case AMDGPU::V_ADDC_U32_e64_dpp: in fixVALUMaskWriteHazard()
2797 case AMDGPU::V_CNDMASK_B16_e64: in fixVALUMaskWriteHazard()
2798 case AMDGPU::V_CNDMASK_B16_e64_dpp: in fixVALUMaskWriteHazard()
2799 case AMDGPU::V_CNDMASK_B32_e64: in fixVALUMaskWriteHazard()
2800 case AMDGPU::V_CNDMASK_B32_e64_dpp: in fixVALUMaskWriteHazard()
2801 case AMDGPU::V_SUBB_U32_e64: in fixVALUMaskWriteHazard()
2802 case AMDGPU::V_SUBB_U32_e64_dpp: in fixVALUMaskWriteHazard()
2803 case AMDGPU::V_SUBBREV_U32_e64: in fixVALUMaskWriteHazard()
2804 case AMDGPU::V_SUBBREV_U32_e64_dpp: { in fixVALUMaskWriteHazard()
2806 const MachineOperand *SSRCOp = TII.getNamedOperand(I, AMDGPU::OpName::src2); in fixVALUMaskWriteHazard()
2818 if (I.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR && in fixVALUMaskWriteHazard()
2819 AMDGPU::DepCtr::decodeFieldSaSdst(I.getOperand(0).getImm()) == 0) in fixVALUMaskWriteHazard()
2835 if (OpReg == AMDGPU::EXEC || in fixVALUMaskWriteHazard()
2836 OpReg == AMDGPU::EXEC_LO || in fixVALUMaskWriteHazard()
2837 OpReg == AMDGPU::EXEC_HI) in fixVALUMaskWriteHazard()
2841 if (OpReg == AMDGPU::VCC || in fixVALUMaskWriteHazard()
2842 OpReg == AMDGPU::VCC_LO || in fixVALUMaskWriteHazard()
2843 OpReg == AMDGPU::VCC_HI) in fixVALUMaskWriteHazard()
2868 TII.get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVALUMaskWriteHazard()
2869 .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0)); in fixVALUMaskWriteHazard()
2872 if (MI->getOpcode() == AMDGPU::S_GETPC_B64) { in fixVALUMaskWriteHazard()