Lines Matching refs:AMDGPU
44 using namespace llvm::AMDGPU;
278 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16); in isRegOrImmWithInt16InputMods()
282 return isRegOrImmWithInputMods(AMDGPU::VS_16RegClassID, MVT::i16); in isRegOrImmWithIntT16InputMods()
286 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32); in isRegOrImmWithInt32InputMods()
290 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i16); in isRegOrInlineImmWithInt16InputMods()
294 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i32); in isRegOrInlineImmWithInt32InputMods()
298 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64); in isRegOrImmWithInt64InputMods()
302 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16); in isRegOrImmWithFP16InputMods()
306 return isRegOrImmWithInputMods(AMDGPU::VS_16RegClassID, MVT::f16); in isRegOrImmWithFPT16InputMods()
310 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32); in isRegOrImmWithFP32InputMods()
314 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64); in isRegOrImmWithFP64InputMods()
318 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f16); in isRegOrInlineImmWithFP16InputMods()
322 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f32); in isRegOrInlineImmWithFP32InputMods()
327 return isRegClass(AMDGPU::VGPR_32RegClassID) || in isVReg()
328 isRegClass(AMDGPU::VReg_64RegClassID) || in isVReg()
329 isRegClass(AMDGPU::VReg_96RegClassID) || in isVReg()
330 isRegClass(AMDGPU::VReg_128RegClassID) || in isVReg()
331 isRegClass(AMDGPU::VReg_160RegClassID) || in isVReg()
332 isRegClass(AMDGPU::VReg_192RegClassID) || in isVReg()
333 isRegClass(AMDGPU::VReg_256RegClassID) || in isVReg()
334 isRegClass(AMDGPU::VReg_512RegClassID) || in isVReg()
335 isRegClass(AMDGPU::VReg_1024RegClassID); in isVReg()
339 return isRegClass(AMDGPU::VGPR_32RegClassID); in isVReg32()
347 return isRegKind() && getReg() == AMDGPU::SGPR_NULL; in isNull()
421 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16); in isSCSrcB16()
429 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32); in isSCSrcB32()
433 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64); in isSCSrcB64()
439 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16); in isSCSrcF16()
447 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32); in isSCSrcF32()
451 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64); in isSCSrcF64()
511 return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) || in isSSrcOrLdsB32()
516 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32); in isVCSrcB32()
520 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64); in isVCSrcB64()
524 return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::i16); in isVCSrcTB16()
528 return isRegOrInlineNoMods(AMDGPU::VS_16_Lo128RegClassID, MVT::i16); in isVCSrcTB16_Lo128()
532 return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::i16); in isVCSrcFake16B16_Lo128()
536 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16); in isVCSrcB16()
544 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32); in isVCSrcF32()
548 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64); in isVCSrcF64()
552 return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::f16); in isVCSrcTF16()
556 return isRegOrInlineNoMods(AMDGPU::VS_16_Lo128RegClassID, MVT::f16); in isVCSrcTF16_Lo128()
560 return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::f16); in isVCSrcFake16F16_Lo128()
564 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16); in isVCSrcF16()
640 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32); in isVISrcB32()
644 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16); in isVISrcB16()
652 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32); in isVISrcF32()
656 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16); in isVISrcF16()
664 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f16); in isVISrc_64F16()
668 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32); in isVISrc_64B32()
672 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i64); in isVISrc_64B64()
676 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f64); in isVISrc_64F64()
680 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32); in isVISrc_64V2FP32()
684 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32); in isVISrc_64V2INT32()
688 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32); in isVISrc_256B32()
692 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32); in isVISrc_256F32()
696 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64); in isVISrc_256B64()
700 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64); in isVISrc_256F64()
704 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i16); in isVISrc_128B16()
712 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i32); in isVISrc_128B32()
716 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f32); in isVISrc_128F32()
720 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32); in isVISrc_256V2FP32()
724 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32); in isVISrc_256V2INT32()
728 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i32); in isVISrc_512B32()
732 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i16); in isVISrc_512B16()
740 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f32); in isVISrc_512F32()
744 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f16); in isVISrc_512F16()
752 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i32); in isVISrc_1024B32()
756 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i16); in isVISrc_1024B16()
764 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f32); in isVISrc_1024F32()
768 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f16); in isVISrc_1024F16()
776 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32); in isAISrcB32()
780 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16); in isAISrcB16()
788 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32); in isAISrcF32()
792 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16); in isAISrcF16()
800 return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::i64); in isAISrc_64B64()
804 return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::f64); in isAISrc_64F64()
808 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32); in isAISrc_128B32()
812 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16); in isAISrc_128B16()
820 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32); in isAISrc_128F32()
824 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16); in isAISrc_128F16()
832 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f16); in isVISrc_128F16()
840 return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::i64); in isAISrc_256B64()
844 return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::f64); in isAISrc_256F64()
848 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32); in isAISrc_512B32()
852 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16); in isAISrc_512B16()
860 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32); in isAISrc_512F32()
864 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16); in isAISrc_512F16()
872 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32); in isAISrc_1024B32()
876 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16); in isAISrc_1024B16()
884 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32); in isAISrc_1024F32()
888 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16); in isAISrc_1024F16()
1406 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in AMDGPUAsmParser()
1434 return AMDGPU::hasMIMG_R128(getSTI()); in hasMIMG_R128()
1438 return AMDGPU::hasPackedD16(getSTI()); in hasPackedD16()
1441 bool hasA16() const { return AMDGPU::hasA16(getSTI()); } in hasA16()
1443 bool hasG16() const { return AMDGPU::hasG16(getSTI()); } in hasG16()
1445 bool hasGDS() const { return AMDGPU::hasGDS(getSTI()); } in hasGDS()
1448 return AMDGPU::isSI(getSTI()); in isSI()
1452 return AMDGPU::isCI(getSTI()); in isCI()
1456 return AMDGPU::isVI(getSTI()); in isVI()
1460 return AMDGPU::isGFX9(getSTI()); in isGFX9()
1465 return AMDGPU::isGFX90A(getSTI()); in isGFX90A()
1469 return AMDGPU::isGFX940(getSTI()); in isGFX940()
1473 return AMDGPU::isGFX9Plus(getSTI()); in isGFX9Plus()
1477 return AMDGPU::isGFX10(getSTI()); in isGFX10()
1480 bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); } in isGFX10Plus()
1483 return AMDGPU::isGFX11(getSTI()); in isGFX11()
1487 return AMDGPU::isGFX11Plus(getSTI()); in isGFX11Plus()
1490 bool isGFX12() const { return AMDGPU::isGFX12(getSTI()); } in isGFX12()
1492 bool isGFX12Plus() const { return AMDGPU::isGFX12Plus(getSTI()); } in isGFX12Plus()
1494 bool isGFX10_AEncoding() const { return AMDGPU::isGFX10_AEncoding(getSTI()); } in isGFX10_AEncoding()
1497 return AMDGPU::isGFX10_BEncoding(getSTI()); in isGFX10_BEncoding()
1501 return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]; in hasInv2PiInlineImm()
1505 return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets]; in hasFlatOffsets()
1509 return getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; in hasArchitectedFlatScratch()
1519 return getFeatureBits()[AMDGPU::FeatureIntClamp]; in hasIntClamp()
1523 return getFeatureBits()[AMDGPU::FeaturePartialNSAEncoding]; in hasPartialNSAEncoding()
1527 return AMDGPU::getNSAMaxSize(getSTI(), HasSampler); in getNSAMaxSize()
1531 return AMDGPU::getMaxNumUserSGPRs(getSTI()); in getMaxNumUserSGPRs()
1534 bool hasKernargPreload() const { return AMDGPU::hasKernargPreload(getSTI()); } in hasKernargPreload()
1883 case AMDGPU::OPERAND_REG_IMM_INT32: in getOpFltSemantics()
1884 case AMDGPU::OPERAND_REG_IMM_FP32: in getOpFltSemantics()
1885 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in getOpFltSemantics()
1886 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in getOpFltSemantics()
1887 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in getOpFltSemantics()
1888 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in getOpFltSemantics()
1889 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in getOpFltSemantics()
1890 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in getOpFltSemantics()
1891 case AMDGPU::OPERAND_REG_IMM_V2FP32: in getOpFltSemantics()
1892 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in getOpFltSemantics()
1893 case AMDGPU::OPERAND_REG_IMM_V2INT32: in getOpFltSemantics()
1894 case AMDGPU::OPERAND_REG_IMM_V2INT16: in getOpFltSemantics()
1895 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in getOpFltSemantics()
1896 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in getOpFltSemantics()
1897 case AMDGPU::OPERAND_KIMM32: in getOpFltSemantics()
1898 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: in getOpFltSemantics()
1900 case AMDGPU::OPERAND_REG_IMM_INT64: in getOpFltSemantics()
1901 case AMDGPU::OPERAND_REG_IMM_FP64: in getOpFltSemantics()
1902 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in getOpFltSemantics()
1903 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in getOpFltSemantics()
1904 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in getOpFltSemantics()
1906 case AMDGPU::OPERAND_REG_IMM_INT16: in getOpFltSemantics()
1907 case AMDGPU::OPERAND_REG_IMM_FP16: in getOpFltSemantics()
1908 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in getOpFltSemantics()
1909 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in getOpFltSemantics()
1910 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in getOpFltSemantics()
1911 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in getOpFltSemantics()
1912 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in getOpFltSemantics()
1913 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in getOpFltSemantics()
1914 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in getOpFltSemantics()
1915 case AMDGPU::OPERAND_REG_IMM_V2FP16: in getOpFltSemantics()
1916 case AMDGPU::OPERAND_KIMM16: in getOpFltSemantics()
1956 return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi); in isInlineableLiteralOp16()
1981 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
1996 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
2003 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
2017 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
2080 return isRegClass(AMDGPU::VGPR_32RegClassID) || in isVRegWithInputMods()
2082 (isRegClass(AMDGPU::VReg_64RegClassID) && in isVRegWithInputMods()
2083 AsmParser->getFeatureBits()[AMDGPU::FeatureDPALU_DPP]); in isVRegWithInputMods()
2087 return isRegClass(IsFake16 ? AMDGPU::VGPR_32_Lo128RegClassID in isT16VRegWithInputMods()
2088 : AMDGPU::VGPR_16_Lo128RegClassID); in isT16VRegWithInputMods()
2095 return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type); in isSDWAOperand()
2118 return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) || in isBoolReg()
2119 (FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32())); in isBoolReg()
2145 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), in addImmOperands()
2161 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2164 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2174 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
2175 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
2176 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
2177 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
2178 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in addLiteralImmOperand()
2179 if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), in addLiteralImmOperand()
2187 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
2206 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
2207 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
2208 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in addLiteralImmOperand()
2209 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
2210 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
2211 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in addLiteralImmOperand()
2212 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in addLiteralImmOperand()
2213 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
2214 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
2215 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in addLiteralImmOperand()
2216 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
2217 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
2218 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
2219 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in addLiteralImmOperand()
2220 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in addLiteralImmOperand()
2221 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in addLiteralImmOperand()
2222 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in addLiteralImmOperand()
2223 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in addLiteralImmOperand()
2224 case AMDGPU::OPERAND_REG_IMM_V2INT16: in addLiteralImmOperand()
2225 case AMDGPU::OPERAND_REG_IMM_V2FP16: in addLiteralImmOperand()
2226 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in addLiteralImmOperand()
2227 case AMDGPU::OPERAND_REG_IMM_V2FP32: in addLiteralImmOperand()
2228 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in addLiteralImmOperand()
2229 case AMDGPU::OPERAND_REG_IMM_V2INT32: in addLiteralImmOperand()
2230 case AMDGPU::OPERAND_KIMM32: in addLiteralImmOperand()
2231 case AMDGPU::OPERAND_KIMM16: in addLiteralImmOperand()
2232 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: { in addLiteralImmOperand()
2243 if (OpTy == AMDGPU::OPERAND_KIMM32 || OpTy == AMDGPU::OPERAND_KIMM16) { in addLiteralImmOperand()
2260 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
2261 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
2262 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in addLiteralImmOperand()
2263 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
2264 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
2265 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in addLiteralImmOperand()
2266 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in addLiteralImmOperand()
2267 case AMDGPU::OPERAND_REG_IMM_V2INT16: in addLiteralImmOperand()
2268 case AMDGPU::OPERAND_REG_IMM_V2FP16: in addLiteralImmOperand()
2269 case AMDGPU::OPERAND_REG_IMM_V2FP32: in addLiteralImmOperand()
2270 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in addLiteralImmOperand()
2271 case AMDGPU::OPERAND_REG_IMM_V2INT32: in addLiteralImmOperand()
2272 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in addLiteralImmOperand()
2273 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: in addLiteralImmOperand()
2275 AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val), in addLiteralImmOperand()
2286 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
2287 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
2288 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
2289 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
2290 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in addLiteralImmOperand()
2291 if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
2297 Val = AMDGPU::isSISrcFPOperand(InstDesc, OpNum) ? (uint64_t)Val << 32 in addLiteralImmOperand()
2304 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
2305 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
2306 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in addLiteralImmOperand()
2307 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
2308 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
2309 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in addLiteralImmOperand()
2310 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in addLiteralImmOperand()
2312 AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), in addLiteralImmOperand()
2323 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
2324 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in addLiteralImmOperand()
2325 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in addLiteralImmOperand()
2326 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: { in addLiteralImmOperand()
2328 assert(AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), in addLiteralImmOperand()
2334 case AMDGPU::OPERAND_KIMM32: in addLiteralImmOperand()
2338 case AMDGPU::OPERAND_KIMM16: in addLiteralImmOperand()
2348 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI()))); in addRegOperands()
2364 return AMDGPU::VGPR_32RegClassID; in getRegClass()
2366 return AMDGPU::VReg_64RegClassID; in getRegClass()
2368 return AMDGPU::VReg_96RegClassID; in getRegClass()
2370 return AMDGPU::VReg_128RegClassID; in getRegClass()
2372 return AMDGPU::VReg_160RegClassID; in getRegClass()
2374 return AMDGPU::VReg_192RegClassID; in getRegClass()
2376 return AMDGPU::VReg_224RegClassID; in getRegClass()
2378 return AMDGPU::VReg_256RegClassID; in getRegClass()
2380 return AMDGPU::VReg_288RegClassID; in getRegClass()
2382 return AMDGPU::VReg_320RegClassID; in getRegClass()
2384 return AMDGPU::VReg_352RegClassID; in getRegClass()
2386 return AMDGPU::VReg_384RegClassID; in getRegClass()
2388 return AMDGPU::VReg_512RegClassID; in getRegClass()
2390 return AMDGPU::VReg_1024RegClassID; in getRegClass()
2396 return AMDGPU::TTMP_32RegClassID; in getRegClass()
2398 return AMDGPU::TTMP_64RegClassID; in getRegClass()
2400 return AMDGPU::TTMP_128RegClassID; in getRegClass()
2402 return AMDGPU::TTMP_256RegClassID; in getRegClass()
2404 return AMDGPU::TTMP_512RegClassID; in getRegClass()
2410 return AMDGPU::SGPR_32RegClassID; in getRegClass()
2412 return AMDGPU::SGPR_64RegClassID; in getRegClass()
2414 return AMDGPU::SGPR_96RegClassID; in getRegClass()
2416 return AMDGPU::SGPR_128RegClassID; in getRegClass()
2418 return AMDGPU::SGPR_160RegClassID; in getRegClass()
2420 return AMDGPU::SGPR_192RegClassID; in getRegClass()
2422 return AMDGPU::SGPR_224RegClassID; in getRegClass()
2424 return AMDGPU::SGPR_256RegClassID; in getRegClass()
2426 return AMDGPU::SGPR_288RegClassID; in getRegClass()
2428 return AMDGPU::SGPR_320RegClassID; in getRegClass()
2430 return AMDGPU::SGPR_352RegClassID; in getRegClass()
2432 return AMDGPU::SGPR_384RegClassID; in getRegClass()
2434 return AMDGPU::SGPR_512RegClassID; in getRegClass()
2440 return AMDGPU::AGPR_32RegClassID; in getRegClass()
2442 return AMDGPU::AReg_64RegClassID; in getRegClass()
2444 return AMDGPU::AReg_96RegClassID; in getRegClass()
2446 return AMDGPU::AReg_128RegClassID; in getRegClass()
2448 return AMDGPU::AReg_160RegClassID; in getRegClass()
2450 return AMDGPU::AReg_192RegClassID; in getRegClass()
2452 return AMDGPU::AReg_224RegClassID; in getRegClass()
2454 return AMDGPU::AReg_256RegClassID; in getRegClass()
2456 return AMDGPU::AReg_288RegClassID; in getRegClass()
2458 return AMDGPU::AReg_320RegClassID; in getRegClass()
2460 return AMDGPU::AReg_352RegClassID; in getRegClass()
2462 return AMDGPU::AReg_384RegClassID; in getRegClass()
2464 return AMDGPU::AReg_512RegClassID; in getRegClass()
2466 return AMDGPU::AReg_1024RegClassID; in getRegClass()
2474 .Case("exec", AMDGPU::EXEC) in getSpecialRegForName()
2475 .Case("vcc", AMDGPU::VCC) in getSpecialRegForName()
2476 .Case("flat_scratch", AMDGPU::FLAT_SCR) in getSpecialRegForName()
2477 .Case("xnack_mask", AMDGPU::XNACK_MASK) in getSpecialRegForName()
2478 .Case("shared_base", AMDGPU::SRC_SHARED_BASE) in getSpecialRegForName()
2479 .Case("src_shared_base", AMDGPU::SRC_SHARED_BASE) in getSpecialRegForName()
2480 .Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT) in getSpecialRegForName()
2481 .Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT) in getSpecialRegForName()
2482 .Case("private_base", AMDGPU::SRC_PRIVATE_BASE) in getSpecialRegForName()
2483 .Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE) in getSpecialRegForName()
2484 .Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT) in getSpecialRegForName()
2485 .Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT) in getSpecialRegForName()
2486 .Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) in getSpecialRegForName()
2487 .Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) in getSpecialRegForName()
2488 .Case("lds_direct", AMDGPU::LDS_DIRECT) in getSpecialRegForName()
2489 .Case("src_lds_direct", AMDGPU::LDS_DIRECT) in getSpecialRegForName()
2490 .Case("m0", AMDGPU::M0) in getSpecialRegForName()
2491 .Case("vccz", AMDGPU::SRC_VCCZ) in getSpecialRegForName()
2492 .Case("src_vccz", AMDGPU::SRC_VCCZ) in getSpecialRegForName()
2493 .Case("execz", AMDGPU::SRC_EXECZ) in getSpecialRegForName()
2494 .Case("src_execz", AMDGPU::SRC_EXECZ) in getSpecialRegForName()
2495 .Case("scc", AMDGPU::SRC_SCC) in getSpecialRegForName()
2496 .Case("src_scc", AMDGPU::SRC_SCC) in getSpecialRegForName()
2497 .Case("tba", AMDGPU::TBA) in getSpecialRegForName()
2498 .Case("tma", AMDGPU::TMA) in getSpecialRegForName()
2499 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO) in getSpecialRegForName()
2500 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI) in getSpecialRegForName()
2501 .Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO) in getSpecialRegForName()
2502 .Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI) in getSpecialRegForName()
2503 .Case("vcc_lo", AMDGPU::VCC_LO) in getSpecialRegForName()
2504 .Case("vcc_hi", AMDGPU::VCC_HI) in getSpecialRegForName()
2505 .Case("exec_lo", AMDGPU::EXEC_LO) in getSpecialRegForName()
2506 .Case("exec_hi", AMDGPU::EXEC_HI) in getSpecialRegForName()
2507 .Case("tma_lo", AMDGPU::TMA_LO) in getSpecialRegForName()
2508 .Case("tma_hi", AMDGPU::TMA_HI) in getSpecialRegForName()
2509 .Case("tba_lo", AMDGPU::TBA_LO) in getSpecialRegForName()
2510 .Case("tba_hi", AMDGPU::TBA_HI) in getSpecialRegForName()
2511 .Case("pc", AMDGPU::PC_REG) in getSpecialRegForName()
2512 .Case("null", AMDGPU::SGPR_NULL) in getSpecialRegForName()
2513 .Default(AMDGPU::NoRegister); in getSpecialRegForName()
2549 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { in AddNextRegisterToList()
2550 Reg = AMDGPU::EXEC; in AddNextRegisterToList()
2554 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { in AddNextRegisterToList()
2555 Reg = AMDGPU::FLAT_SCR; in AddNextRegisterToList()
2559 if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) { in AddNextRegisterToList()
2560 Reg = AMDGPU::XNACK_MASK; in AddNextRegisterToList()
2564 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { in AddNextRegisterToList()
2565 Reg = AMDGPU::VCC; in AddNextRegisterToList()
2569 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { in AddNextRegisterToList()
2570 Reg = AMDGPU::TBA; in AddNextRegisterToList()
2574 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { in AddNextRegisterToList()
2575 Reg = AMDGPU::TMA; in AddNextRegisterToList()
2659 return getSpecialRegForName(Str) != AMDGPU::NoRegister; in isRegister()
2682 return AMDGPU::NoRegister; in getRegularReg()
2689 return AMDGPU::NoRegister; in getRegularReg()
2696 return AMDGPU::NoRegister; in getRegularReg()
2779 return AMDGPU::NoRegister; in ParseRegularReg()
2794 SubReg = AMDGPU::lo16; in ParseRegularReg()
2796 SubReg = AMDGPU::hi16; in ParseRegularReg()
2801 return AMDGPU::NoRegister; in ParseRegularReg()
2807 return AMDGPU::NoRegister; in ParseRegularReg()
2816 unsigned Reg = AMDGPU::NoRegister; in ParseRegList()
2821 return AMDGPU::NoRegister; in ParseRegList()
2828 return AMDGPU::NoRegister; in ParseRegList()
2831 return AMDGPU::NoRegister; in ParseRegList()
2842 return AMDGPU::NoRegister; in ParseRegList()
2846 return AMDGPU::NoRegister; in ParseRegList()
2850 return AMDGPU::NoRegister; in ParseRegList()
2853 return AMDGPU::NoRegister; in ParseRegList()
2858 return AMDGPU::NoRegister; in ParseRegList()
2871 Reg = AMDGPU::NoRegister; in ParseAMDGPURegister()
2875 if (Reg == AMDGPU::NoRegister) in ParseAMDGPURegister()
2882 if (Reg == AMDGPU::NoRegister) { in ParseAMDGPURegister()
2888 if (Reg == AMDGPU::SGPR_NULL) { in ParseAMDGPURegister()
2902 Reg = AMDGPU::NoRegister; in ParseAMDGPURegister()
2939 if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6) in updateGprCountSymbols()
3332 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in checkTargetMatchPredicate()
3333 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in checkTargetMatchPredicate()
3336 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel); in checkTargetMatchPredicate()
3338 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { in checkTargetMatchPredicate()
3409 case AMDGPU::FLAT_SCR: in findImplicitSGPRReadInVOP()
3410 case AMDGPU::VCC: in findImplicitSGPRReadInVOP()
3411 case AMDGPU::VCC_LO: in findImplicitSGPRReadInVOP()
3412 case AMDGPU::VCC_HI: in findImplicitSGPRReadInVOP()
3413 case AMDGPU::M0: in findImplicitSGPRReadInVOP()
3419 return AMDGPU::NoRegister; in findImplicitSGPRReadInVOP()
3430 if (!AMDGPU::isSISrcOperand(Desc, OpIdx) || in isInlineConstant()
3431 AMDGPU::isKImmOperand(Desc, OpIdx)) { in isInlineConstant()
3438 auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx); in isInlineConstant()
3442 return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm()); in isInlineConstant()
3444 return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm()); in isInlineConstant()
3447 if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 || in isInlineConstant()
3448 OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 || in isInlineConstant()
3449 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16) in isInlineConstant()
3450 return AMDGPU::isInlinableIntLiteral(Val); in isInlineConstant()
3452 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 || in isInlineConstant()
3453 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 || in isInlineConstant()
3454 OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16) in isInlineConstant()
3455 return AMDGPU::isInlinableLiteralV2I16(Val); in isInlineConstant()
3457 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 || in isInlineConstant()
3458 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 || in isInlineConstant()
3459 OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16) in isInlineConstant()
3460 return AMDGPU::isInlinableLiteralV2F16(Val); in isInlineConstant()
3462 return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm()); in isInlineConstant()
3475 case AMDGPU::V_LSHLREV_B64_e64: in getConstantBusLimit()
3476 case AMDGPU::V_LSHLREV_B64_gfx10: in getConstantBusLimit()
3477 case AMDGPU::V_LSHLREV_B64_e64_gfx11: in getConstantBusLimit()
3478 case AMDGPU::V_LSHLREV_B64_e32_gfx12: in getConstantBusLimit()
3479 case AMDGPU::V_LSHLREV_B64_e64_gfx12: in getConstantBusLimit()
3480 case AMDGPU::V_LSHRREV_B64_e64: in getConstantBusLimit()
3481 case AMDGPU::V_LSHRREV_B64_gfx10: in getConstantBusLimit()
3482 case AMDGPU::V_LSHRREV_B64_e64_gfx11: in getConstantBusLimit()
3483 case AMDGPU::V_LSHRREV_B64_e64_gfx12: in getConstantBusLimit()
3484 case AMDGPU::V_ASHRREV_I64_e64: in getConstantBusLimit()
3485 case AMDGPU::V_ASHRREV_I64_gfx10: in getConstantBusLimit()
3486 case AMDGPU::V_ASHRREV_I64_e64_gfx11: in getConstantBusLimit()
3487 case AMDGPU::V_ASHRREV_I64_e64_gfx12: in getConstantBusLimit()
3488 case AMDGPU::V_LSHL_B64_e64: in getConstantBusLimit()
3489 case AMDGPU::V_LSHR_B64_e64: in getConstantBusLimit()
3490 case AMDGPU::V_ASHR_I64_e64: in getConstantBusLimit()
3547 unsigned LastSGPR = AMDGPU::NoRegister; in validateConstantBusLimitations()
3559 if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::imm)) { in validateConstantBusLimitations()
3566 if (SGPRUsed != AMDGPU::NoRegister) { in validateConstantBusLimitations()
3604 unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx); in validateConstantBusLimitations()
3646 bool SkipSrc = Opcode == AMDGPU::V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12; in validateVOPDRegBankConstraints()
3678 int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp); in validateIntClampSupported()
3698 int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata); in validateMIMGDataSize()
3699 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGDataSize()
3700 int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe); in validateMIMGDataSize()
3707 unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx); in validateMIMGDataSize()
3717 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGDataSize()
3744 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGAddrSize()
3746 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in validateMIMGAddrSize()
3747 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in validateMIMGAddrSize()
3748 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in validateMIMGAddrSize()
3749 int RSrcOpName = Desc.TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc in validateMIMGAddrSize()
3750 : AMDGPU::OpName::rsrc; in validateMIMGAddrSize()
3751 int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RSrcOpName); in validateMIMGAddrSize()
3752 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGAddrSize()
3753 int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16); in validateMIMGAddrSize()
3768 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in validateMIMGAddrSize()
3772 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; in validateMIMGAddrSize()
3775 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16()); in validateMIMGAddrSize()
3783 AMDGPU::getRegOperandSize(getMRI(), Desc, VAddrLastIdx) / 4; in validateMIMGAddrSize()
3815 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGAtomicDMask()
3833 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGGatherDMask()
3851 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGMSAA()
3852 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in validateMIMGMSAA()
3853 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in validateMIMGMSAA()
3858 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGMSAA()
3862 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in validateMIMGMSAA()
3870 case AMDGPU::V_MOVRELS_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3871 case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3872 case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3891 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateMovrels()
3915 if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi) in validateMAIAccWrite()
3918 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateMAIAccWrite()
3966 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in validateMFMA()
4007 for (auto Name : {AMDGPU::OpName::src0_modifiers, in validateDivScale()
4008 AMDGPU::OpName::src2_modifiers, in validateDivScale()
4009 AMDGPU::OpName::src2_modifiers}) { in validateDivScale()
4010 if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name)) in validateDivScale()
4028 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGD16()
4040 case AMDGPU::V_SUBREV_F32_e32: in IsRevOpcode()
4041 case AMDGPU::V_SUBREV_F32_e64: in IsRevOpcode()
4042 case AMDGPU::V_SUBREV_F32_e32_gfx10: in IsRevOpcode()
4043 case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7: in IsRevOpcode()
4044 case AMDGPU::V_SUBREV_F32_e32_vi: in IsRevOpcode()
4045 case AMDGPU::V_SUBREV_F32_e64_gfx10: in IsRevOpcode()
4046 case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7: in IsRevOpcode()
4047 case AMDGPU::V_SUBREV_F32_e64_vi: in IsRevOpcode()
4049 case AMDGPU::V_SUBREV_CO_U32_e32: in IsRevOpcode()
4050 case AMDGPU::V_SUBREV_CO_U32_e64: in IsRevOpcode()
4051 case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7: in IsRevOpcode()
4052 case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7: in IsRevOpcode()
4054 case AMDGPU::V_SUBBREV_U32_e32: in IsRevOpcode()
4055 case AMDGPU::V_SUBBREV_U32_e64: in IsRevOpcode()
4056 case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7: in IsRevOpcode()
4057 case AMDGPU::V_SUBBREV_U32_e32_vi: in IsRevOpcode()
4058 case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7: in IsRevOpcode()
4059 case AMDGPU::V_SUBBREV_U32_e64_vi: in IsRevOpcode()
4061 case AMDGPU::V_SUBREV_U32_e32: in IsRevOpcode()
4062 case AMDGPU::V_SUBREV_U32_e64: in IsRevOpcode()
4063 case AMDGPU::V_SUBREV_U32_e32_gfx9: in IsRevOpcode()
4064 case AMDGPU::V_SUBREV_U32_e32_vi: in IsRevOpcode()
4065 case AMDGPU::V_SUBREV_U32_e64_gfx9: in IsRevOpcode()
4066 case AMDGPU::V_SUBREV_U32_e64_vi: in IsRevOpcode()
4068 case AMDGPU::V_SUBREV_F16_e32: in IsRevOpcode()
4069 case AMDGPU::V_SUBREV_F16_e64: in IsRevOpcode()
4070 case AMDGPU::V_SUBREV_F16_e32_gfx10: in IsRevOpcode()
4071 case AMDGPU::V_SUBREV_F16_e32_vi: in IsRevOpcode()
4072 case AMDGPU::V_SUBREV_F16_e64_gfx10: in IsRevOpcode()
4073 case AMDGPU::V_SUBREV_F16_e64_vi: in IsRevOpcode()
4075 case AMDGPU::V_SUBREV_U16_e32: in IsRevOpcode()
4076 case AMDGPU::V_SUBREV_U16_e64: in IsRevOpcode()
4077 case AMDGPU::V_SUBREV_U16_e32_vi: in IsRevOpcode()
4078 case AMDGPU::V_SUBREV_U16_e64_vi: in IsRevOpcode()
4080 case AMDGPU::V_SUBREV_CO_U32_e32_gfx9: in IsRevOpcode()
4081 case AMDGPU::V_SUBREV_CO_U32_e64_gfx10: in IsRevOpcode()
4082 case AMDGPU::V_SUBREV_CO_U32_e64_gfx9: in IsRevOpcode()
4084 case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9: in IsRevOpcode()
4085 case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9: in IsRevOpcode()
4087 case AMDGPU::V_SUBREV_NC_U32_e32_gfx10: in IsRevOpcode()
4088 case AMDGPU::V_SUBREV_NC_U32_e64_gfx10: in IsRevOpcode()
4090 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in IsRevOpcode()
4091 case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10: in IsRevOpcode()
4093 case AMDGPU::V_LSHRREV_B32_e32: in IsRevOpcode()
4094 case AMDGPU::V_LSHRREV_B32_e64: in IsRevOpcode()
4095 case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7: in IsRevOpcode()
4096 case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7: in IsRevOpcode()
4097 case AMDGPU::V_LSHRREV_B32_e32_vi: in IsRevOpcode()
4098 case AMDGPU::V_LSHRREV_B32_e64_vi: in IsRevOpcode()
4099 case AMDGPU::V_LSHRREV_B32_e32_gfx10: in IsRevOpcode()
4100 case AMDGPU::V_LSHRREV_B32_e64_gfx10: in IsRevOpcode()
4102 case AMDGPU::V_ASHRREV_I32_e32: in IsRevOpcode()
4103 case AMDGPU::V_ASHRREV_I32_e64: in IsRevOpcode()
4104 case AMDGPU::V_ASHRREV_I32_e32_gfx10: in IsRevOpcode()
4105 case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7: in IsRevOpcode()
4106 case AMDGPU::V_ASHRREV_I32_e32_vi: in IsRevOpcode()
4107 case AMDGPU::V_ASHRREV_I32_e64_gfx10: in IsRevOpcode()
4108 case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7: in IsRevOpcode()
4109 case AMDGPU::V_ASHRREV_I32_e64_vi: in IsRevOpcode()
4111 case AMDGPU::V_LSHLREV_B32_e32: in IsRevOpcode()
4112 case AMDGPU::V_LSHLREV_B32_e64: in IsRevOpcode()
4113 case AMDGPU::V_LSHLREV_B32_e32_gfx10: in IsRevOpcode()
4114 case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7: in IsRevOpcode()
4115 case AMDGPU::V_LSHLREV_B32_e32_vi: in IsRevOpcode()
4116 case AMDGPU::V_LSHLREV_B32_e64_gfx10: in IsRevOpcode()
4117 case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7: in IsRevOpcode()
4118 case AMDGPU::V_LSHLREV_B32_e64_vi: in IsRevOpcode()
4120 case AMDGPU::V_LSHLREV_B16_e32: in IsRevOpcode()
4121 case AMDGPU::V_LSHLREV_B16_e64: in IsRevOpcode()
4122 case AMDGPU::V_LSHLREV_B16_e32_vi: in IsRevOpcode()
4123 case AMDGPU::V_LSHLREV_B16_e64_vi: in IsRevOpcode()
4124 case AMDGPU::V_LSHLREV_B16_gfx10: in IsRevOpcode()
4126 case AMDGPU::V_LSHRREV_B16_e32: in IsRevOpcode()
4127 case AMDGPU::V_LSHRREV_B16_e64: in IsRevOpcode()
4128 case AMDGPU::V_LSHRREV_B16_e32_vi: in IsRevOpcode()
4129 case AMDGPU::V_LSHRREV_B16_e64_vi: in IsRevOpcode()
4130 case AMDGPU::V_LSHRREV_B16_gfx10: in IsRevOpcode()
4132 case AMDGPU::V_ASHRREV_I16_e32: in IsRevOpcode()
4133 case AMDGPU::V_ASHRREV_I16_e64: in IsRevOpcode()
4134 case AMDGPU::V_ASHRREV_I16_e32_vi: in IsRevOpcode()
4135 case AMDGPU::V_ASHRREV_I16_e64_vi: in IsRevOpcode()
4136 case AMDGPU::V_ASHRREV_I16_gfx10: in IsRevOpcode()
4138 case AMDGPU::V_LSHLREV_B64_e64: in IsRevOpcode()
4139 case AMDGPU::V_LSHLREV_B64_gfx10: in IsRevOpcode()
4140 case AMDGPU::V_LSHLREV_B64_vi: in IsRevOpcode()
4142 case AMDGPU::V_LSHRREV_B64_e64: in IsRevOpcode()
4143 case AMDGPU::V_LSHRREV_B64_gfx10: in IsRevOpcode()
4144 case AMDGPU::V_LSHRREV_B64_vi: in IsRevOpcode()
4146 case AMDGPU::V_ASHRREV_I64_e64: in IsRevOpcode()
4147 case AMDGPU::V_ASHRREV_I64_gfx10: in IsRevOpcode()
4148 case AMDGPU::V_ASHRREV_I64_vi: in IsRevOpcode()
4150 case AMDGPU::V_PK_LSHLREV_B16: in IsRevOpcode()
4151 case AMDGPU::V_PK_LSHLREV_B16_gfx10: in IsRevOpcode()
4152 case AMDGPU::V_PK_LSHLREV_B16_vi: in IsRevOpcode()
4154 case AMDGPU::V_PK_LSHRREV_B16: in IsRevOpcode()
4155 case AMDGPU::V_PK_LSHRREV_B16_gfx10: in IsRevOpcode()
4156 case AMDGPU::V_PK_LSHRREV_B16_vi: in IsRevOpcode()
4157 case AMDGPU::V_PK_ASHRREV_I16: in IsRevOpcode()
4158 case AMDGPU::V_PK_ASHRREV_I16_gfx10: in IsRevOpcode()
4159 case AMDGPU::V_PK_ASHRREV_I16_vi: in IsRevOpcode()
4212 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset); in validateOffset()
4250 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset); in validateFlatOffset()
4262 unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI()); in validateFlatOffset()
4297 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset); in validateSMEMOffset()
4306 bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode); in validateSMEMOffset()
4307 if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) || in validateSMEMOffset()
4308 AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer)) in validateSMEMOffset()
4325 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateSOPLiteral()
4326 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateSOPLiteral()
4339 if (AMDGPU::isSISrcOperand(Desc, OpIdx)) { in validateSOPLiteral()
4358 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in validateOpSel()
4368 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in validateOpSel()
4373 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi); in validateOpSel()
4383 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in validateOpSel()
4393 assert(OpName == AMDGPU::OpName::neg_lo || OpName == AMDGPU::OpName::neg_hi); in validateNeg()
4406 int NegIdx = AMDGPU::getNamedOperandIdx(Opc, OpName); in validateNeg()
4417 int SrcMods[3] = {AMDGPU::OpName::src0_modifiers, in validateNeg()
4418 AMDGPU::OpName::src1_modifiers, in validateNeg()
4419 AMDGPU::OpName::src2_modifiers}; in validateNeg()
4422 if (!AMDGPU::hasNamedOperand(Opc, SrcMods[i])) { in validateNeg()
4434 int DppCtrlIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dpp_ctrl); in validateDPP()
4438 if (!AMDGPU::isLegalDPALU_DPPControl(DppCtrl) && in validateDPP()
4439 AMDGPU::isDPALU_DPP(MII.get(Opc))) { in validateDPP()
4447 int Dpp8Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dpp8); in validateDPP()
4451 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); in validateDPP()
4470 return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) || in validateVccOperand()
4471 (FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO); in validateVccOperand()
4502 bool IsFP64 = AMDGPU::isSISrcFPOperand(Desc, OpIdx) && in validateVOPLiteral()
4503 AMDGPU::getOperandSize(Desc.operands()[OpIdx]) == 8; in validateVOPLiteral()
4504 bool IsValid32Op = AMDGPU::isValid32BitLiteral(Value, IsFP64); in validateVOPLiteral()
4543 int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx); in IsAGPROperand()
4551 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in IsAGPROperand()
4553 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in IsAGPROperand()
4564 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in validateAGPRLdSt()
4565 : AMDGPU::OpName::vdata; in validateAGPRLdSt()
4568 int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI); in validateAGPRLdSt()
4572 int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI); in validateAGPRLdSt()
4578 if (FB[AMDGPU::FeatureGFX90AInsts]) { in validateAGPRLdSt()
4589 if (!FB[AMDGPU::FeatureGFX90AInsts]) in validateVGPRAlign()
4593 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign()
4594 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in validateVGPRAlign()
4600 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in validateVGPRAlign()
4604 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4606 if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1)) in validateVGPRAlign()
4625 int BlgpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::blgp); in validateBLGP()
4634 if (FB[AMDGPU::FeatureGFX940Insts]) { in validateBLGP()
4636 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd: in validateBLGP()
4637 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd: in validateBLGP()
4638 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd: in validateBLGP()
4639 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd: in validateBLGP()
4660 if (Opc != AMDGPU::S_WAITCNT_EXPCNT_gfx11 && in validateWaitCnt()
4661 Opc != AMDGPU::S_WAITCNT_LGKMCNT_gfx11 && in validateWaitCnt()
4662 Opc != AMDGPU::S_WAITCNT_VMCNT_gfx11 && in validateWaitCnt()
4663 Opc != AMDGPU::S_WAITCNT_VSCNT_gfx11) in validateWaitCnt()
4666 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst); in validateWaitCnt()
4669 if (Reg == AMDGPU::SGPR_NULL) in validateWaitCnt()
4688 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::gds); in validateDS()
4704 if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) in validateGWS()
4708 if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi && in validateGWS()
4709 Opc != AMDGPU::DS_GWS_SEMA_BR_vi) in validateGWS()
4713 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateGWS()
4715 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0); in validateGWS()
4718 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()
4731 int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), in validateCoherencyBits()
4732 AMDGPU::OpName::cpol); in validateCoherencyBits()
4748 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) { in validateCoherencyBits()
4795 const unsigned TH = CPol & AMDGPU::CPol::TH; in validateTHAndScopeBits()
4796 const unsigned Scope = CPol & AMDGPU::CPol::SCOPE; in validateTHAndScopeBits()
4809 (!(TH & AMDGPU::CPol::TH_ATOMIC_RETURN))) in validateTHAndScopeBits()
4816 ((TH == AMDGPU::CPol::TH_NT_RT) || (TH == AMDGPU::CPol::TH_RT_NT) || in validateTHAndScopeBits()
4817 (TH == AMDGPU::CPol::TH_NT_HT))) in validateTHAndScopeBits()
4820 if (TH == AMDGPU::CPol::TH_BYPASS) { in validateTHAndScopeBits()
4821 if ((Scope != AMDGPU::CPol::SCOPE_SYS && in validateTHAndScopeBits()
4822 CPol & AMDGPU::CPol::TH_REAL_BYPASS) || in validateTHAndScopeBits()
4823 (Scope == AMDGPU::CPol::SCOPE_SYS && in validateTHAndScopeBits()
4824 !(CPol & AMDGPU::CPol::TH_REAL_BYPASS))) in validateTHAndScopeBits()
4833 if (!(CPol & AMDGPU::CPol::TH_TYPE_ATOMIC)) in validateTHAndScopeBits()
4836 if (!(CPol & AMDGPU::CPol::TH_TYPE_STORE)) in validateTHAndScopeBits()
4839 if (!(CPol & AMDGPU::CPol::TH_TYPE_LOAD)) in validateTHAndScopeBits()
4908 if (!validateNeg(Inst, AMDGPU::OpName::neg_lo)) { in validateInstruction()
4913 if (!validateNeg(Inst, AMDGPU::OpName::neg_hi)) { in validateInstruction()
4967 Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts] in validateInstruction()
5049 if (isGFX10Plus() && getFeatureBits()[AMDGPU::FeatureWavefrontSize64] && in checkUnsupportedInstruction()
5050 !getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) { in checkUnsupportedInstruction()
5053 FeaturesWS32.flip(AMDGPU::FeatureWavefrontSize64) in checkUnsupportedInstruction()
5054 .flip(AMDGPU::FeatureWavefrontSize32); in checkUnsupportedInstruction()
5683 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) in ParseAMDKernelCodeTValue()
5686 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64]) in ParseAMDKernelCodeTValue()
5695 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) in ParseAMDKernelCodeTValue()
5698 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64]) in ParseAMDKernelCodeTValue()
5726 AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI()); in ParseDirectiveAMDKernelCodeT()
5834 if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin, in ParseDirectivePALMetadataBegin()
5835 AMDGPU::PALMD::AssemblerDirectiveEnd, String)) in ParseDirectivePALMetadataBegin()
5890 unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI()); in ParseDirectiveAMDGPULDS()
5938 if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin) in ParseDirective()
5950 if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin) { in ParseDirective()
5976 if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo)) in subtargetHasRegister()
5980 if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo)) in subtargetHasRegister()
5984 case AMDGPU::SRC_SHARED_BASE_LO: in subtargetHasRegister()
5985 case AMDGPU::SRC_SHARED_BASE: in subtargetHasRegister()
5986 case AMDGPU::SRC_SHARED_LIMIT_LO: in subtargetHasRegister()
5987 case AMDGPU::SRC_SHARED_LIMIT: in subtargetHasRegister()
5988 case AMDGPU::SRC_PRIVATE_BASE_LO: in subtargetHasRegister()
5989 case AMDGPU::SRC_PRIVATE_BASE: in subtargetHasRegister()
5990 case AMDGPU::SRC_PRIVATE_LIMIT_LO: in subtargetHasRegister()
5991 case AMDGPU::SRC_PRIVATE_LIMIT: in subtargetHasRegister()
5993 case AMDGPU::SRC_POPS_EXITING_WAVE_ID: in subtargetHasRegister()
5995 case AMDGPU::TBA: in subtargetHasRegister()
5996 case AMDGPU::TBA_LO: in subtargetHasRegister()
5997 case AMDGPU::TBA_HI: in subtargetHasRegister()
5998 case AMDGPU::TMA: in subtargetHasRegister()
5999 case AMDGPU::TMA_LO: in subtargetHasRegister()
6000 case AMDGPU::TMA_HI: in subtargetHasRegister()
6002 case AMDGPU::XNACK_MASK: in subtargetHasRegister()
6003 case AMDGPU::XNACK_MASK_LO: in subtargetHasRegister()
6004 case AMDGPU::XNACK_MASK_HI: in subtargetHasRegister()
6006 case AMDGPU::SGPR_NULL: in subtargetHasRegister()
6020 case AMDGPU::FLAT_SCR: in subtargetHasRegister()
6021 case AMDGPU::FLAT_SCR_LO: in subtargetHasRegister()
6022 case AMDGPU::FLAT_SCR_HI: in subtargetHasRegister()
6031 if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo)) in subtargetHasRegister()
6274 .Case("nt", AMDGPU::CPol::NT) in getCPolKind()
6275 .Case("sc0", AMDGPU::CPol::SC0) in getCPolKind()
6276 .Case("sc1", AMDGPU::CPol::SC1) in getCPolKind()
6281 .Case("dlc", AMDGPU::CPol::DLC) in getCPolKind()
6282 .Case("glc", AMDGPU::CPol::GLC) in getCPolKind()
6283 .Case("scc", AMDGPU::CPol::SCC) in getCPolKind()
6284 .Case("slc", AMDGPU::CPol::SLC) in getCPolKind()
6342 if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC) in parseCPol()
6345 if (!isGFX90A() && CPol == AMDGPU::CPol::SCC) in parseCPol()
6367 Scope = AMDGPU::CPol::SCOPE_CU; // default; in parseScope()
6378 .Case("SCOPE_CU", AMDGPU::CPol::SCOPE_CU) in parseScope()
6379 .Case("SCOPE_SE", AMDGPU::CPol::SCOPE_SE) in parseScope()
6380 .Case("SCOPE_DEV", AMDGPU::CPol::SCOPE_DEV) in parseScope()
6381 .Case("SCOPE_SYS", AMDGPU::CPol::SCOPE_SYS) in parseScope()
6391 TH = AMDGPU::CPol::TH_RT; // default in parseTH()
6400 TH = AMDGPU::CPol::TH_RT; in parseTH()
6406 TH = AMDGPU::CPol::TH_TYPE_ATOMIC; in parseTH()
6409 TH = AMDGPU::CPol::TH_TYPE_LOAD; in parseTH()
6412 TH = AMDGPU::CPol::TH_TYPE_STORE; in parseTH()
6418 TH |= AMDGPU::CPol::TH_REAL_BYPASS; in parseTH()
6421 if (TH & AMDGPU::CPol::TH_TYPE_ATOMIC) in parseTH()
6423 .Case("RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN) in parseTH()
6424 .Case("RT", AMDGPU::CPol::TH_RT) in parseTH()
6425 .Case("RT_RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN) in parseTH()
6426 .Case("NT", AMDGPU::CPol::TH_ATOMIC_NT) in parseTH()
6427 .Case("NT_RETURN", AMDGPU::CPol::TH_ATOMIC_NT | in parseTH()
6428 AMDGPU::CPol::TH_ATOMIC_RETURN) in parseTH()
6429 .Case("CASCADE_RT", AMDGPU::CPol::TH_ATOMIC_CASCADE) in parseTH()
6430 .Case("CASCADE_NT", AMDGPU::CPol::TH_ATOMIC_CASCADE | in parseTH()
6431 AMDGPU::CPol::TH_ATOMIC_NT) in parseTH()
6435 .Case("RT", AMDGPU::CPol::TH_RT) in parseTH()
6436 .Case("NT", AMDGPU::CPol::TH_NT) in parseTH()
6437 .Case("HT", AMDGPU::CPol::TH_HT) in parseTH()
6438 .Case("LU", AMDGPU::CPol::TH_LU) in parseTH()
6439 .Case("RT_WB", AMDGPU::CPol::TH_RT_WB) in parseTH()
6440 .Case("NT_RT", AMDGPU::CPol::TH_NT_RT) in parseTH()
6441 .Case("RT_NT", AMDGPU::CPol::TH_RT_NT) in parseTH()
6442 .Case("NT_HT", AMDGPU::CPol::TH_NT_HT) in parseTH()
6443 .Case("NT_WB", AMDGPU::CPol::TH_NT_WB) in parseTH()
6444 .Case("BYPASS", AMDGPU::CPol::TH_BYPASS) in parseTH()
6534 using namespace llvm::AMDGPU::MTBUFFormat; in parseDfmtNfmt()
6566 using namespace llvm::AMDGPU::MTBUFFormat; in parseUfmt()
6584 using namespace llvm::AMDGPU::MTBUFFormat; in matchDfmtNfmt()
6606 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicSplitFormat()
6643 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicUnifiedFormat()
6657 using namespace llvm::AMDGPU::MTBUFFormat; in parseNumericFormat()
6669 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicOrNumericFormat()
6696 using namespace llvm::AMDGPU::MTBUFFormat; in parseFORMAT()
6800 Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister)); in cvtExp()
6823 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister); in cvtExp()
6824 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister); in cvtExp()
6828 if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) { in cvtExp()
6845 const AMDGPU::IsaVersion ISA, in encodeCnt()
6879 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseCnt()
6914 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseSWaitCnt()
7045 using namespace llvm::AMDGPU::DepCtr; in parseDepCtr()
7082 using namespace llvm::AMDGPU::DepCtr; in parseDepCtr()
7112 using namespace llvm::AMDGPU::Hwreg; in parseHwregBody()
7148 using namespace llvm::AMDGPU::Hwreg; in validateHwreg()
7176 using namespace llvm::AMDGPU::Hwreg; in parseHwreg()
7214 using namespace llvm::AMDGPU::SendMsg; in parseSendMsgBody()
7250 using namespace llvm::AMDGPU::SendMsg; in validateSendMsg()
7293 using namespace llvm::AMDGPU::SendMsg; in parseSendMsg()
7391 using namespace llvm::AMDGPU::Exp; in parseExpTgt()
7650 using namespace llvm::AMDGPU::Swizzle; in encodeBitmaskPerm()
7695 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleQuadPerm()
7711 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBroadcast()
7739 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleReverse()
7761 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleSwap()
7783 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBitmaskPerm()
7845 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleMacro()
7905 using namespace llvm::AMDGPU::VGPRIndexMode; in parseGPRIdxMacro()
7949 using namespace llvm::AMDGPU::VGPRIndexMode; in parseGPRIdxMode()
8028 IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC; in cvtMubufImpl()
8033 int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode()); in cvtMubufImpl()
8166 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3DstOpSelOnly()
8171 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3DstOpSelOnly()
8172 AMDGPU::OpName::src1, in cvtVOP3DstOpSelOnly()
8173 AMDGPU::OpName::src2 }; in cvtVOP3DstOpSelOnly()
8174 for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]); in cvtVOP3DstOpSelOnly()
8182 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in cvtVOP3DstOpSelOnly()
8203 Desc.operands()[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS in isRegOrImmWithInputMods()
8238 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::high)) in cvtVOP3Interp()
8242 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp)) in cvtVOP3Interp()
8246 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod)) in cvtVOP3Interp()
8275 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVINTERP()
8284 const int Ops[] = { AMDGPU::OpName::src0, in cvtVINTERP()
8285 AMDGPU::OpName::src1, in cvtVINTERP()
8286 AMDGPU::OpName::src2 }; in cvtVINTERP()
8287 const int ModOps[] = { AMDGPU::OpName::src0_modifiers, in cvtVINTERP()
8288 AMDGPU::OpName::src1_modifiers, in cvtVINTERP()
8289 AMDGPU::OpName::src2_modifiers }; in cvtVINTERP()
8294 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]); in cvtVINTERP()
8298 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); in cvtVINTERP()
8303 if (ModOps[J] == AMDGPU::OpName::src0_modifiers && in cvtVINTERP()
8334 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp)) in cvtVOP3()
8338 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod)) in cvtVOP3()
8348 std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers)); in cvtVOP3()
8368 if (Opc == AMDGPU::V_CVT_SR_BF8_F32_vi || in cvtVOP3P()
8369 Opc == AMDGPU::V_CVT_SR_FP8_F32_vi || in cvtVOP3P()
8370 Opc == AMDGPU::V_CVT_SR_BF8_F32_e64_gfx12 || in cvtVOP3P()
8371 Opc == AMDGPU::V_CVT_SR_FP8_F32_e64_gfx12) { in cvtVOP3P()
8378 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in) && in cvtVOP3P()
8379 !(Opc == AMDGPU::V_CVT_PK_BF8_F32_e64_dpp_gfx12 || in cvtVOP3P()
8380 Opc == AMDGPU::V_CVT_PK_FP8_F32_e64_dpp_gfx12 || in cvtVOP3P()
8381 Opc == AMDGPU::V_CVT_PK_BF8_F32_e64_dpp8_gfx12 || in cvtVOP3P()
8382 Opc == AMDGPU::V_CVT_PK_FP8_F32_e64_dpp8_gfx12)) { in cvtVOP3P()
8390 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3P()
8395 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi); in cvtVOP3P()
8402 int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo); in cvtVOP3P()
8406 int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi); in cvtVOP3P()
8410 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3P()
8411 AMDGPU::OpName::src1, in cvtVOP3P()
8412 AMDGPU::OpName::src2 }; in cvtVOP3P()
8413 const int ModOps[] = { AMDGPU::OpName::src0_modifiers, in cvtVOP3P()
8414 AMDGPU::OpName::src1_modifiers, in cvtVOP3P()
8415 AMDGPU::OpName::src2_modifiers }; in cvtVOP3P()
8435 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]); in cvtVOP3P()
8439 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); in cvtVOP3P()
8470 if (AMDGPU::getNamedOperandIdx(Opc, OpName) != -1) in addSrcModifiersAndSrc()
8480 addSrcModifiersAndSrc(Inst, Operands, 2, Opc, AMDGPU::OpName::src0_modifiers); in cvtSWMMAC()
8481 addSrcModifiersAndSrc(Inst, Operands, 3, Opc, AMDGPU::OpName::src1_modifiers); in cvtSWMMAC()
8491 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::index_key_8bit)) in cvtSWMMAC()
8495 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::index_key_16bit)) in cvtSWMMAC()
8499 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp)) in cvtSWMMAC()
8572 using namespace AMDGPU::DPP; in isDPPCtrl()
8644 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId); in parseDimId()
8767 using namespace AMDGPU::DPP; in parseDPPCtrlSel()
8814 using namespace AMDGPU::DPP; in parseDPPCtrl()
8857 int OldIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old); in cvtVOP3DPP()
8859 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers); in cvtVOP3DPP()
8883 int VdstInIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in); in cvtVOP3DPP()
8888 bool IsVOP3CvtSrDpp = Opc == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 || in cvtVOP3DPP()
8889 Opc == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12 || in cvtVOP3DPP()
8890 Opc == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 || in cvtVOP3DPP()
8891 Opc == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12; in cvtVOP3DPP()
8924 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp)) in cvtVOP3DPP()
8927 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod)) in cvtVOP3DPP()
8934 else if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { in cvtVOP3DPP()
8940 using namespace llvm::AMDGPU::DPP; in cvtVOP3DPP()
8948 if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) in cvtVOP3DPP()
9009 using namespace llvm::AMDGPU::DPP; in cvtDPP()
9015 if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) { in cvtDPP()
9029 using namespace llvm::AMDGPU::SDWA; in parseSDWASel()
9058 using namespace llvm::AMDGPU::SDWA; in parseSDWADstUnused()
9106 using namespace llvm::AMDGPU::SDWA; in cvtSDWA()
9121 (Op.getReg() == AMDGPU::VCC || Op.getReg() == AMDGPU::VCC_LO)) { in cvtSDWA()
9150 if (Opc != AMDGPU::V_NOP_sdwa_gfx10 && Opc != AMDGPU::V_NOP_sdwa_gfx9 && in cvtSDWA()
9151 Opc != AMDGPU::V_NOP_sdwa_vi) { in cvtSDWA()
9155 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp)) in cvtSDWA()
9159 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod)) in cvtSDWA()
9163 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel)) in cvtSDWA()
9167 if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused)) in cvtSDWA()
9178 if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod)) in cvtSDWA()
9188 if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp)) in cvtSDWA()
9201 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in cvtSDWA()
9202 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in cvtSDWA()
9205 it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2)); in cvtSDWA()