Lines Matching refs:AMDGPU
128 if (AMDGPU::isTrue16Inst(Op)) in isShrinkable()
130 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
140 if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) || in isShrinkable()
141 !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) || in isShrinkable()
142 !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) || in isShrinkable()
143 !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0)) { in isShrinkable()
151 int DPP32 = AMDGPU::getDPPOp32(Op); in getDPPOp()
154 int E32 = AMDGPU::getVOPe32(Op); in getDPPOp()
155 DPP32 = (E32 == -1) ? -1 : AMDGPU::getDPPOp32(E32); in getDPPOp()
161 DPP64 = AMDGPU::getDPPOp64(Op); in getDPPOp()
178 case AMDGPU::IMPLICIT_DEF: in getOldOpndValue()
180 case AMDGPU::COPY: in getOldOpndValue()
181 case AMDGPU::V_MOV_B32_e32: in getOldOpndValue()
182 case AMDGPU::V_MOV_B64_PSEUDO: in getOldOpndValue()
183 case AMDGPU::V_MOV_B64_e32: in getOldOpndValue()
184 case AMDGPU::V_MOV_B64_e64: { in getOldOpndValue()
209 assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp || in createDPPInst()
210 MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp || in createDPPInst()
211 MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO); in createDPPInst()
220 int OrigOpE32 = AMDGPU::getVOPe32(OrigOp); in createDPPInst()
222 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in createDPPInst()
224 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in createDPPInst()
241 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
245 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
253 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old); in createDPPInst()
259 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
277 auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers); in createDPPInst()
279 assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp, in createDPPInst()
280 AMDGPU::OpName::src0_modifiers)); in createDPPInst()
285 } else if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::src0_modifiers)) { in createDPPInst()
289 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
301 auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers); in createDPPInst()
303 assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp, in createDPPInst()
304 AMDGPU::OpName::src1_modifiers)); in createDPPInst()
309 } else if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::src1_modifiers)) { in createDPPInst()
313 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
334 auto *Mod2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers); in createDPPInst()
337 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src2_modifiers)); in createDPPInst()
343 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst()
345 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
356 auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp); in createDPPInst()
357 if (ClampOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::clamp)) { in createDPPInst()
360 auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in); in createDPPInst()
362 AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::vdst_in)) { in createDPPInst()
365 auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod); in createDPPInst()
366 if (OmodOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::omod)) { in createDPPInst()
372 TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) { in createDPPInst()
385 if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::op_sel)) in createDPPInst()
389 TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) { in createDPPInst()
403 if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::op_sel_hi)) in createDPPInst()
406 auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo); in createDPPInst()
407 if (NegOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::neg_lo)) { in createDPPInst()
410 auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi); in createDPPInst()
411 if (NegHiOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::neg_hi)) { in createDPPInst()
415 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); in createDPPInst()
416 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask)); in createDPPInst()
417 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask)); in createDPPInst()
433 case AMDGPU::V_ADD_U32_e32: in isIdentityValue()
434 case AMDGPU::V_ADD_U32_e64: in isIdentityValue()
435 case AMDGPU::V_ADD_CO_U32_e32: in isIdentityValue()
436 case AMDGPU::V_ADD_CO_U32_e64: in isIdentityValue()
437 case AMDGPU::V_OR_B32_e32: in isIdentityValue()
438 case AMDGPU::V_OR_B32_e64: in isIdentityValue()
439 case AMDGPU::V_SUBREV_U32_e32: in isIdentityValue()
440 case AMDGPU::V_SUBREV_U32_e64: in isIdentityValue()
441 case AMDGPU::V_SUBREV_CO_U32_e32: in isIdentityValue()
442 case AMDGPU::V_SUBREV_CO_U32_e64: in isIdentityValue()
443 case AMDGPU::V_MAX_U32_e32: in isIdentityValue()
444 case AMDGPU::V_MAX_U32_e64: in isIdentityValue()
445 case AMDGPU::V_XOR_B32_e32: in isIdentityValue()
446 case AMDGPU::V_XOR_B32_e64: in isIdentityValue()
450 case AMDGPU::V_AND_B32_e32: in isIdentityValue()
451 case AMDGPU::V_AND_B32_e64: in isIdentityValue()
452 case AMDGPU::V_MIN_U32_e32: in isIdentityValue()
453 case AMDGPU::V_MIN_U32_e64: in isIdentityValue()
458 case AMDGPU::V_MIN_I32_e32: in isIdentityValue()
459 case AMDGPU::V_MIN_I32_e64: in isIdentityValue()
464 case AMDGPU::V_MAX_I32_e32: in isIdentityValue()
465 case AMDGPU::V_MAX_I32_e64: in isIdentityValue()
470 case AMDGPU::V_MUL_I32_I24_e32: in isIdentityValue()
471 case AMDGPU::V_MUL_I32_I24_e64: in isIdentityValue()
472 case AMDGPU::V_MUL_U32_U24_e32: in isIdentityValue()
473 case AMDGPU::V_MUL_U32_U24_e64: in isIdentityValue()
486 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
496 auto MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in createDPPInst()
519 assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp || in combineDPPMov()
520 MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp || in combineDPPMov()
521 MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO); in combineDPPMov()
524 auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in combineDPPMov()
537 if (MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO || in combineDPPMov()
538 MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp) { in combineDPPMov()
539 auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl); in combineDPPMov()
541 if (!AMDGPU::isLegalDPALU_DPPControl(DppCtrl->getImm())) { in combineDPPMov()
549 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in combineDPPMov()
551 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in combineDPPMov()
556 auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl); in combineDPPMov()
560 auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old); in combineDPPMov()
561 auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in combineDPPMov()
615 TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg); in combineDPPMov()
635 assert((TII->get(OrigOp).getSize() != 4 || !AMDGPU::isTrue16Inst(OrigOp)) && in combineDPPMov()
637 if (OrigOp == AMDGPU::REG_SEQUENCE) { in combineDPPMov()
675 if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) { in combineDPPMov()
680 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov()
681 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in combineDPPMov()
687 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov()
759 if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) { in runOnMachineFunction()
762 } else if (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO || in runOnMachineFunction()
763 MI.getOpcode() == AMDGPU::V_MOV_B64_dpp) { in runOnMachineFunction()