Lines Matching refs:AMDGPU
25 using namespace llvm::AMDGPU;
107 if (AMDGPU::isGFX12(STI) && IsVBuffer) in printOffset()
124 AMDGPU::isGFX12(STI); in printFlatOffset()
127 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI))); in printFlatOffset()
180 if (AMDGPU::isGFX12Plus(STI)) { in printCPol()
191 O << ((AMDGPU::isGFX940(STI) && in printCPol()
195 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc"); in printCPol()
196 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
198 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
199 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc"); in printCPol()
220 if (TH & AMDGPU::CPol::TH_ATOMIC_CASCADE) { in printTH()
221 if (Scope >= AMDGPU::CPol::SCOPE_DEV) in printTH()
222 O << "CASCADE" << (TH & AMDGPU::CPol::TH_ATOMIC_NT ? "_NT" : "_RT"); in printTH()
225 } else if (TH & AMDGPU::CPol::TH_ATOMIC_NT) in printTH()
226 O << "NT" << (TH & AMDGPU::CPol::TH_ATOMIC_RETURN ? "_RETURN" : ""); in printTH()
227 else if (TH & AMDGPU::CPol::TH_ATOMIC_RETURN) in printTH()
232 if (!IsStore && TH == AMDGPU::CPol::TH_RESERVED) in printTH()
240 case AMDGPU::CPol::TH_NT: in printTH()
243 case AMDGPU::CPol::TH_HT: in printTH()
246 case AMDGPU::CPol::TH_BYPASS: // or LU or RT_WB in printTH()
247 O << (Scope == AMDGPU::CPol::SCOPE_SYS ? "BYPASS" in printTH()
250 case AMDGPU::CPol::TH_NT_RT: in printTH()
253 case AMDGPU::CPol::TH_RT_NT: in printTH()
256 case AMDGPU::CPol::TH_NT_HT: in printTH()
259 case AMDGPU::CPol::TH_NT_WB: in printTH()
300 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in printDim()
309 if (STI.hasFeature(AMDGPU::FeatureR128A16)) in printR128A16()
323 using namespace llvm::AMDGPU::MTBUFFormat; in printSymbolicFormat()
326 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); in printSymbolicFormat()
330 if (AMDGPU::isGFX10Plus(STI)) { in printSymbolicFormat()
366 case AMDGPU::FP_REG: in printRegOperand()
367 case AMDGPU::SP_REG: in printRegOperand()
368 case AMDGPU::PRIVATE_RSRC_REG: in printRegOperand()
370 case AMDGPU::SCC: in printRegOperand()
406 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: in printVOPDst()
407 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: in printVOPDst()
408 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in printVOPDst()
409 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: in printVOPDst()
410 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: in printVOPDst()
411 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: in printVOPDst()
412 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: in printVOPDst()
413 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: in printVOPDst()
414 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: in printVOPDst()
415 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: in printVOPDst()
416 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: in printVOPDst()
417 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: in printVOPDst()
418 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11: in printVOPDst()
419 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11: in printVOPDst()
420 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11: in printVOPDst()
421 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11: in printVOPDst()
422 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11: in printVOPDst()
423 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11: in printVOPDst()
424 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11: in printVOPDst()
425 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11: in printVOPDst()
426 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11: in printVOPDst()
427 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12: in printVOPDst()
428 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12: in printVOPDst()
429 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12: in printVOPDst()
430 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12: in printVOPDst()
431 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12: in printVOPDst()
432 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12: in printVOPDst()
433 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12: in printVOPDst()
434 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12: in printVOPDst()
435 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12: in printVOPDst()
443 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
483 else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateFloat16()
518 case AMDGPU::OPERAND_REG_IMM_V2INT16: in printImmediateV216()
519 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in printImmediateV216()
520 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in printImmediateV216()
524 case AMDGPU::OPERAND_REG_IMM_V2FP16: in printImmediateV216()
525 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in printImmediateV216()
526 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in printImmediateV216()
560 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateFloat32()
611 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediate64()
614 assert(AMDGPU::isValid32BitLiteral(Imm, true)); in printImmediate64()
632 if (AMDGPU::isGFX940(STI)) { in printBLGP()
634 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd: in printBLGP()
635 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd: in printBLGP()
636 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd: in printBLGP()
637 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd: in printBLGP()
672 printRegOperand(STI.hasFeature(AMDGPU::FeatureWavefrontSize64) in printDefaultVccOperand()
673 ? AMDGPU::VCC in printDefaultVccOperand()
674 : AMDGPU::VCC_LO, in printDefaultVccOperand()
712 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || in needsImpliedVcc()
713 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)); in needsImpliedVcc()
722 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOperand()
729 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || in printOperand()
730 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO))) in printOperand()
766 case AMDGPU::OPERAND_REG_IMM_INT32: in printRegularOperand()
767 case AMDGPU::OPERAND_REG_IMM_FP32: in printRegularOperand()
768 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in printRegularOperand()
769 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in printRegularOperand()
770 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in printRegularOperand()
771 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in printRegularOperand()
772 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in printRegularOperand()
773 case AMDGPU::OPERAND_REG_IMM_V2INT32: in printRegularOperand()
774 case AMDGPU::OPERAND_REG_IMM_V2FP32: in printRegularOperand()
775 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in printRegularOperand()
776 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in printRegularOperand()
778 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: in printRegularOperand()
781 case AMDGPU::OPERAND_REG_IMM_INT64: in printRegularOperand()
782 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in printRegularOperand()
785 case AMDGPU::OPERAND_REG_IMM_FP64: in printRegularOperand()
786 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in printRegularOperand()
787 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in printRegularOperand()
790 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in printRegularOperand()
791 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in printRegularOperand()
792 case AMDGPU::OPERAND_REG_IMM_INT16: in printRegularOperand()
795 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in printRegularOperand()
796 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in printRegularOperand()
797 case AMDGPU::OPERAND_REG_IMM_FP16: in printRegularOperand()
798 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in printRegularOperand()
801 case AMDGPU::OPERAND_REG_IMM_V2INT16: in printRegularOperand()
802 case AMDGPU::OPERAND_REG_IMM_V2FP16: in printRegularOperand()
803 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in printRegularOperand()
804 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in printRegularOperand()
805 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in printRegularOperand()
806 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in printRegularOperand()
832 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()
851 case AMDGPU::V_CNDMASK_B32_e32_gfx10: in printRegularOperand()
852 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: in printRegularOperand()
853 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: in printRegularOperand()
854 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in printRegularOperand()
855 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: in printRegularOperand()
856 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: in printRegularOperand()
857 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: in printRegularOperand()
858 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10: in printRegularOperand()
859 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: in printRegularOperand()
860 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: in printRegularOperand()
861 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: in printRegularOperand()
862 case AMDGPU::V_CNDMASK_B32_e32_gfx11: in printRegularOperand()
863 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11: in printRegularOperand()
864 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11: in printRegularOperand()
865 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11: in printRegularOperand()
866 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11: in printRegularOperand()
867 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11: in printRegularOperand()
868 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11: in printRegularOperand()
869 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11: in printRegularOperand()
870 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11: in printRegularOperand()
871 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11: in printRegularOperand()
872 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11: in printRegularOperand()
873 case AMDGPU::V_CNDMASK_B32_e32_gfx12: in printRegularOperand()
874 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12: in printRegularOperand()
875 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12: in printRegularOperand()
876 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12: in printRegularOperand()
877 case AMDGPU::V_CNDMASK_B32_dpp_gfx12: in printRegularOperand()
878 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12: in printRegularOperand()
879 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12: in printRegularOperand()
880 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12: in printRegularOperand()
881 case AMDGPU::V_CNDMASK_B32_dpp8_gfx12: in printRegularOperand()
882 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12: in printRegularOperand()
883 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12: in printRegularOperand()
884 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12: in printRegularOperand()
886 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7: in printRegularOperand()
887 case AMDGPU::V_CNDMASK_B32_e32_vi: in printRegularOperand()
888 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printRegularOperand()
889 AMDGPU::OpName::src1)) in printRegularOperand()
896 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); in printRegularOperand()
946 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10: in printOperandAndFPInputMods()
947 case AMDGPU::V_CNDMASK_B32_dpp_gfx10: in printOperandAndFPInputMods()
948 case AMDGPU::V_CNDMASK_B32_dpp_gfx11: in printOperandAndFPInputMods()
950 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1)) in printOperandAndFPInputMods()
975 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
976 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
977 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
978 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printOperandAndIntInputMods()
979 AMDGPU::OpName::src1)) in printOperandAndIntInputMods()
988 if (!AMDGPU::isGFX10Plus(STI)) in printDPP8()
1002 using namespace AMDGPU::DPP; in printDPPCtrl()
1007 if (!AMDGPU::isLegalDPALU_DPPControl(Imm) && AMDGPU::isDPALU_DPP(Desc)) { in printDPPCtrl()
1029 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1035 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1041 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1047 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1057 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1063 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1070 if (AMDGPU::isGFX90A(STI)) { in printDPPCtrl()
1072 } else if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1082 if (!AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1118 using namespace llvm::AMDGPU::DPP; in printDppFI()
1127 using namespace llvm::AMDGPU::SDWA; in printSDWASel()
1166 using namespace llvm::AMDGPU::SDWA; in printSDWADstUnused()
1182 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
1185 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); in printExpSrcN()
1224 using namespace llvm::AMDGPU::Exp; in printExpTgt()
1264 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0}, in printPackedModifier()
1265 {AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1}, in printPackedModifier()
1266 {AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}}; in printPackedModifier()
1270 if (!AMDGPU::hasNamedOperand(Opc, Src)) in printPackedModifier()
1273 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, SrcMod); in printPackedModifier()
1285 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers, in printPackedModifier()
1286 AMDGPU::OpName::src2_modifiers}) { in printPackedModifier()
1287 int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName); in printPackedModifier()
1327 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOpSel()
1336 auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOpSel()
1337 auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers); in printOpSel()
1422 using namespace llvm::AMDGPU::VGPRIndexMode; in printGPRIdxMode()
1485 using namespace llvm::AMDGPU::SendMsg; in printSendMsg()
1517 using namespace llvm::AMDGPU::Swizzle; in printSwizzleBitmask()
1549 using namespace llvm::AMDGPU::Swizzle; in printSwizzle()
1619 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); in printSWaitCnt()
1654 using namespace llvm::AMDGPU::DepCtr; in printDepCtr()
1727 using namespace llvm::AMDGPU::Hwreg; in printHwreg()