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/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-pair-mma.c18 __builtin_mma_assemble_acc(&res, vc, vc, vc, vc); in test1()
59 __builtin_vsx_assemble_pair(&res, vc, vc); in test3()
137 __builtin_mma_xvi4ger8(&vq, vc, vc); in test8()
151 __builtin_mma_xvi8ger4(&vq, vc, vc); in test9()
165 __builtin_mma_xvi16ger2(&vq, vc, vc); in test10()
179 __builtin_mma_xvi16ger2s(&vq, vc, vc); in test11()
193 __builtin_mma_xvf16ger2(&vq, vc, vc); in test12()
207 __builtin_mma_xvf32ger(&vq, vc, vc); in test13()
339 __builtin_mma_xvi4ger8pp(&vq, vc, vc); in test22()
355 __builtin_mma_xvi8ger4pp(&vq, vc, vc); in test23()
[all …]
H A Dbuiltins-ppc-pair-mma-types.c61 void testVQLocal(int *ptr, vector unsigned char vc) { in testVQLocal() argument
67 __builtin_mma_xvi4ger8(&vq3, vc, vc); in testVQLocal()
139 void testVPLocal(int *ptr, vector unsigned char vc) { in testVPLocal() argument
143 __builtin_vsx_assemble_pair(&vp2, vc, vc); in testVPLocal()
144 __builtin_vsx_build_pair(&vp2, vc, vc); in testVPLocal()
147 __builtin_mma_xvf64ger(&vq, vp3, vc); in testVPLocal()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dswaps-le-2.ll14 ; vector char vc = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
23 ; vcr = (vector char){vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5],
24 ; vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5]};
38 @vc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i…
48 %0 = load <16 x i8>, <16 x i8>* @vc, align 8
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dvsra-sdnode.ll12 ret <vscale x 1 x i8> %vc
24 ret <vscale x 1 x i8> %vc
36 ret <vscale x 1 x i8> %vc
46 ret <vscale x 2 x i8> %vc
58 ret <vscale x 2 x i8> %vc
70 ret <vscale x 2 x i8> %vc
80 ret <vscale x 4 x i8> %vc
92 ret <vscale x 4 x i8> %vc
104 ret <vscale x 4 x i8> %vc
114 ret <vscale x 8 x i8> %vc
[all …]
H A Dvfsub-sdnode.ll14 ret <vscale x 1 x half> %vc
26 ret <vscale x 1 x half> %vc
36 ret <vscale x 2 x half> %vc
48 ret <vscale x 2 x half> %vc
58 ret <vscale x 4 x half> %vc
70 ret <vscale x 4 x half> %vc
80 ret <vscale x 8 x half> %vc
92 ret <vscale x 8 x half> %vc
104 ret <vscale x 8 x half> %vc
114 ret <vscale x 16 x half> %vc
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H A Dvfadd-sdnode.ll14 ret <vscale x 1 x half> %vc
26 ret <vscale x 1 x half> %vc
36 ret <vscale x 2 x half> %vc
48 ret <vscale x 2 x half> %vc
58 ret <vscale x 4 x half> %vc
70 ret <vscale x 4 x half> %vc
80 ret <vscale x 8 x half> %vc
92 ret <vscale x 8 x half> %vc
104 ret <vscale x 8 x half> %vc
114 ret <vscale x 16 x half> %vc
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H A Dvfdiv-sdnode.ll14 ret <vscale x 1 x half> %vc
26 ret <vscale x 1 x half> %vc
36 ret <vscale x 2 x half> %vc
48 ret <vscale x 2 x half> %vc
58 ret <vscale x 4 x half> %vc
70 ret <vscale x 4 x half> %vc
80 ret <vscale x 8 x half> %vc
92 ret <vscale x 8 x half> %vc
104 ret <vscale x 8 x half> %vc
114 ret <vscale x 16 x half> %vc
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H A Dvfmul-sdnode.ll14 ret <vscale x 1 x half> %vc
26 ret <vscale x 1 x half> %vc
36 ret <vscale x 2 x half> %vc
48 ret <vscale x 2 x half> %vc
58 ret <vscale x 4 x half> %vc
70 ret <vscale x 4 x half> %vc
80 ret <vscale x 8 x half> %vc
92 ret <vscale x 8 x half> %vc
104 ret <vscale x 8 x half> %vc
114 ret <vscale x 16 x half> %vc
[all …]
H A Dsetcc-fp.ll17 ret <vscale x 8 x i1> %vc
29 ret <vscale x 8 x i1> %vc
41 ret <vscale x 8 x i1> %vc
51 ret <vscale x 8 x i1> %vc
63 ret <vscale x 8 x i1> %vc
73 ret <vscale x 8 x i1> %vc
85 ret <vscale x 8 x i1> %vc
97 ret <vscale x 8 x i1> %vc
107 ret <vscale x 8 x i1> %vc
119 ret <vscale x 8 x i1> %vc
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H A Dsetcc-integer.ll14 ret <vscale x 3 x i1> %vc
26 ret <vscale x 3 x i1> %vc
38 ret <vscale x 3 x i1> %vc
48 ret <vscale x 8 x i1> %vc
60 ret <vscale x 8 x i1> %vc
72 ret <vscale x 8 x i1> %vc
84 ret <vscale x 8 x i1> %vc
96 ret <vscale x 8 x i1> %vc
108 ret <vscale x 8 x i1> %vc
118 ret <vscale x 8 x i1> %vc
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H A Dvxor-sdnode.ll12 ret <vscale x 1 x i8> %vc
24 ret <vscale x 1 x i8> %vc
36 ret <vscale x 1 x i8> %vc
48 ret <vscale x 1 x i8> %vc
61 ret <vscale x 1 x i8> %vc
71 ret <vscale x 2 x i8> %vc
83 ret <vscale x 2 x i8> %vc
95 ret <vscale x 2 x i8> %vc
107 ret <vscale x 2 x i8> %vc
120 ret <vscale x 2 x i8> %vc
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H A Dvand-sdnode.ll12 ret <vscale x 1 x i8> %vc
24 ret <vscale x 1 x i8> %vc
36 ret <vscale x 1 x i8> %vc
48 ret <vscale x 1 x i8> %vc
61 ret <vscale x 1 x i8> %vc
71 ret <vscale x 2 x i8> %vc
83 ret <vscale x 2 x i8> %vc
95 ret <vscale x 2 x i8> %vc
107 ret <vscale x 2 x i8> %vc
120 ret <vscale x 2 x i8> %vc
[all …]
H A Dvmarith-sdnode.ll12 ret <vscale x 1 x i1> %vc
22 ret <vscale x 2 x i1> %vc
32 ret <vscale x 4 x i1> %vc
42 ret <vscale x 8 x i1> %vc
52 ret <vscale x 16 x i1> %vc
62 ret <vscale x 1 x i1> %vc
72 ret <vscale x 2 x i1> %vc
82 ret <vscale x 4 x i1> %vc
92 ret <vscale x 8 x i1> %vc
112 ret <vscale x 1 x i1> %vc
[all …]
H A Dvshl-sdnode.ll14 ret <vscale x 1 x i8> %vc
26 ret <vscale x 1 x i8> %vc
38 ret <vscale x 2 x i8> %vc
50 ret <vscale x 2 x i8> %vc
62 ret <vscale x 4 x i8> %vc
74 ret <vscale x 4 x i8> %vc
86 ret <vscale x 8 x i8> %vc
98 ret <vscale x 8 x i8> %vc
110 ret <vscale x 16 x i8> %vc
122 ret <vscale x 16 x i8> %vc
[all …]
H A Dvmul-sdnode.ll15 ret <vscale x 1 x i8> %vc
27 ret <vscale x 1 x i8> %vc
40 ret <vscale x 1 x i8> %vc
50 ret <vscale x 2 x i8> %vc
62 ret <vscale x 2 x i8> %vc
75 ret <vscale x 2 x i8> %vc
85 ret <vscale x 4 x i8> %vc
97 ret <vscale x 4 x i8> %vc
110 ret <vscale x 4 x i8> %vc
120 ret <vscale x 8 x i8> %vc
[all …]
H A Dvsrl-sdnode.ll14 ret <vscale x 1 x i8> %vc
26 ret <vscale x 1 x i8> %vc
38 ret <vscale x 2 x i8> %vc
50 ret <vscale x 2 x i8> %vc
62 ret <vscale x 4 x i8> %vc
74 ret <vscale x 4 x i8> %vc
86 ret <vscale x 8 x i8> %vc
98 ret <vscale x 8 x i8> %vc
110 ret <vscale x 16 x i8> %vc
122 ret <vscale x 16 x i8> %vc
[all …]
H A Dvadd-sdnode.ll14 ret <vscale x 1 x i8> %vc
26 ret <vscale x 1 x i8> %vc
38 ret <vscale x 1 x i8> %vc
53 ret <vscale x 1 x i8> %vc
65 ret <vscale x 2 x i8> %vc
77 ret <vscale x 2 x i8> %vc
89 ret <vscale x 2 x i8> %vc
101 ret <vscale x 4 x i8> %vc
113 ret <vscale x 4 x i8> %vc
125 ret <vscale x 4 x i8> %vc
[all …]
H A Dvsub-sdnode.ll12 ret <vscale x 1 x i8> %vc
24 ret <vscale x 1 x i8> %vc
37 ret <vscale x 1 x i8> %vc
52 ret <vscale x 1 x i8> %vc
62 ret <vscale x 2 x i8> %vc
74 ret <vscale x 2 x i8> %vc
87 ret <vscale x 2 x i8> %vc
97 ret <vscale x 4 x i8> %vc
109 ret <vscale x 4 x i8> %vc
122 ret <vscale x 4 x i8> %vc
[all …]
H A Dvselect-int-rv32.ll11 ret <vscale x 1 x i8> %vc
23 ret <vscale x 1 x i8> %vc
35 ret <vscale x 1 x i8> %vc
45 ret <vscale x 2 x i8> %vc
57 ret <vscale x 2 x i8> %vc
69 ret <vscale x 2 x i8> %vc
79 ret <vscale x 3 x i8> %vc
91 ret <vscale x 3 x i8> %vc
103 ret <vscale x 3 x i8> %vc
113 ret <vscale x 4 x i8> %vc
[all …]
H A Dvselect-int-rv64.ll11 ret <vscale x 1 x i8> %vc
23 ret <vscale x 1 x i8> %vc
35 ret <vscale x 1 x i8> %vc
45 ret <vscale x 2 x i8> %vc
57 ret <vscale x 2 x i8> %vc
69 ret <vscale x 2 x i8> %vc
79 ret <vscale x 3 x i8> %vc
91 ret <vscale x 3 x i8> %vc
103 ret <vscale x 3 x i8> %vc
113 ret <vscale x 4 x i8> %vc
[all …]
H A Dvor-sdnode.ll14 ret <vscale x 1 x i8> %vc
26 ret <vscale x 1 x i8> %vc
38 ret <vscale x 1 x i8> %vc
51 ret <vscale x 1 x i8> %vc
63 ret <vscale x 2 x i8> %vc
75 ret <vscale x 2 x i8> %vc
87 ret <vscale x 2 x i8> %vc
100 ret <vscale x 2 x i8> %vc
112 ret <vscale x 4 x i8> %vc
124 ret <vscale x 4 x i8> %vc
[all …]
H A Dvrsub-sdnode.ll14 ret <vscale x 1 x i8> %vc
26 ret <vscale x 1 x i8> %vc
38 ret <vscale x 2 x i8> %vc
50 ret <vscale x 2 x i8> %vc
62 ret <vscale x 4 x i8> %vc
74 ret <vscale x 4 x i8> %vc
86 ret <vscale x 8 x i8> %vc
98 ret <vscale x 8 x i8> %vc
110 ret <vscale x 16 x i8> %vc
122 ret <vscale x 16 x i8> %vc
[all …]
H A Dvmin-sdnode.ll13 ret <vscale x 1 x i8> %vc
26 ret <vscale x 1 x i8> %vc
40 ret <vscale x 1 x i8> %vc
51 ret <vscale x 2 x i8> %vc
64 ret <vscale x 2 x i8> %vc
78 ret <vscale x 2 x i8> %vc
89 ret <vscale x 4 x i8> %vc
102 ret <vscale x 4 x i8> %vc
116 ret <vscale x 4 x i8> %vc
127 ret <vscale x 8 x i8> %vc
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H A Dvminu-sdnode.ll13 ret <vscale x 1 x i8> %vc
26 ret <vscale x 1 x i8> %vc
40 ret <vscale x 1 x i8> %vc
51 ret <vscale x 2 x i8> %vc
64 ret <vscale x 2 x i8> %vc
78 ret <vscale x 2 x i8> %vc
89 ret <vscale x 4 x i8> %vc
102 ret <vscale x 4 x i8> %vc
116 ret <vscale x 4 x i8> %vc
127 ret <vscale x 8 x i8> %vc
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H A Dvmaxu-sdnode.ll13 ret <vscale x 1 x i8> %vc
26 ret <vscale x 1 x i8> %vc
40 ret <vscale x 1 x i8> %vc
51 ret <vscale x 2 x i8> %vc
64 ret <vscale x 2 x i8> %vc
78 ret <vscale x 2 x i8> %vc
89 ret <vscale x 4 x i8> %vc
102 ret <vscale x 4 x i8> %vc
116 ret <vscale x 4 x i8> %vc
127 ret <vscale x 8 x i8> %vc
[all …]

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