1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64NOM 4 5; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 6; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64M 7 8define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) { 9; CHECK-LABEL: vmul_vv_nxv1i8: 10; CHECK: # %bb.0: 11; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 12; CHECK-NEXT: vmul.vv v8, v8, v9 13; CHECK-NEXT: ret 14 %vc = mul <vscale x 1 x i8> %va, %vb 15 ret <vscale x 1 x i8> %vc 16} 17 18define <vscale x 1 x i8> @vmul_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) { 19; CHECK-LABEL: vmul_vx_nxv1i8: 20; CHECK: # %bb.0: 21; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 22; CHECK-NEXT: vmul.vx v8, v8, a0 23; CHECK-NEXT: ret 24 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 25 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 26 %vc = mul <vscale x 1 x i8> %va, %splat 27 ret <vscale x 1 x i8> %vc 28} 29 30define <vscale x 1 x i8> @vmul_vi_nxv1i8_0(<vscale x 1 x i8> %va) { 31; CHECK-LABEL: vmul_vi_nxv1i8_0: 32; CHECK: # %bb.0: 33; CHECK-NEXT: li a0, -7 34; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 35; CHECK-NEXT: vmul.vx v8, v8, a0 36; CHECK-NEXT: ret 37 %head = insertelement <vscale x 1 x i8> poison, i8 -7, i32 0 38 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 39 %vc = mul <vscale x 1 x i8> %va, %splat 40 ret <vscale x 1 x i8> %vc 41} 42 43define <vscale x 2 x i8> @vmul_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) { 44; CHECK-LABEL: vmul_vv_nxv2i8: 45; CHECK: # %bb.0: 46; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 47; CHECK-NEXT: vmul.vv v8, v8, v9 48; CHECK-NEXT: ret 49 %vc = mul <vscale x 2 x i8> %va, %vb 50 ret <vscale x 2 x i8> %vc 51} 52 53define <vscale x 2 x i8> @vmul_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) { 54; CHECK-LABEL: vmul_vx_nxv2i8: 55; CHECK: # %bb.0: 56; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 57; CHECK-NEXT: vmul.vx v8, v8, a0 58; CHECK-NEXT: ret 59 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 60 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer 61 %vc = mul <vscale x 2 x i8> %va, %splat 62 ret <vscale x 2 x i8> %vc 63} 64 65define <vscale x 2 x i8> @vmul_vi_nxv2i8_0(<vscale x 2 x i8> %va) { 66; CHECK-LABEL: vmul_vi_nxv2i8_0: 67; CHECK: # %bb.0: 68; CHECK-NEXT: li a0, -7 69; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 70; CHECK-NEXT: vmul.vx v8, v8, a0 71; CHECK-NEXT: ret 72 %head = insertelement <vscale x 2 x i8> poison, i8 -7, i32 0 73 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer 74 %vc = mul <vscale x 2 x i8> %va, %splat 75 ret <vscale x 2 x i8> %vc 76} 77 78define <vscale x 4 x i8> @vmul_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) { 79; CHECK-LABEL: vmul_vv_nxv4i8: 80; CHECK: # %bb.0: 81; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 82; CHECK-NEXT: vmul.vv v8, v8, v9 83; CHECK-NEXT: ret 84 %vc = mul <vscale x 4 x i8> %va, %vb 85 ret <vscale x 4 x i8> %vc 86} 87 88define <vscale x 4 x i8> @vmul_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) { 89; CHECK-LABEL: vmul_vx_nxv4i8: 90; CHECK: # %bb.0: 91; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 92; CHECK-NEXT: vmul.vx v8, v8, a0 93; CHECK-NEXT: ret 94 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0 95 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer 96 %vc = mul <vscale x 4 x i8> %va, %splat 97 ret <vscale x 4 x i8> %vc 98} 99 100define <vscale x 4 x i8> @vmul_vi_nxv4i8_0(<vscale x 4 x i8> %va) { 101; CHECK-LABEL: vmul_vi_nxv4i8_0: 102; CHECK: # %bb.0: 103; CHECK-NEXT: li a0, -7 104; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 105; CHECK-NEXT: vmul.vx v8, v8, a0 106; CHECK-NEXT: ret 107 %head = insertelement <vscale x 4 x i8> poison, i8 -7, i32 0 108 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer 109 %vc = mul <vscale x 4 x i8> %va, %splat 110 ret <vscale x 4 x i8> %vc 111} 112 113define <vscale x 8 x i8> @vmul_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 114; CHECK-LABEL: vmul_vv_nxv8i8: 115; CHECK: # %bb.0: 116; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 117; CHECK-NEXT: vmul.vv v8, v8, v9 118; CHECK-NEXT: ret 119 %vc = mul <vscale x 8 x i8> %va, %vb 120 ret <vscale x 8 x i8> %vc 121} 122 123define <vscale x 8 x i8> @vmul_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) { 124; CHECK-LABEL: vmul_vx_nxv8i8: 125; CHECK: # %bb.0: 126; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 127; CHECK-NEXT: vmul.vx v8, v8, a0 128; CHECK-NEXT: ret 129 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 130 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 131 %vc = mul <vscale x 8 x i8> %va, %splat 132 ret <vscale x 8 x i8> %vc 133} 134 135define <vscale x 8 x i8> @vmul_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 136; CHECK-LABEL: vmul_vi_nxv8i8_0: 137; CHECK: # %bb.0: 138; CHECK-NEXT: li a0, -7 139; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 140; CHECK-NEXT: vmul.vx v8, v8, a0 141; CHECK-NEXT: ret 142 %head = insertelement <vscale x 8 x i8> poison, i8 -7, i32 0 143 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 144 %vc = mul <vscale x 8 x i8> %va, %splat 145 ret <vscale x 8 x i8> %vc 146} 147 148define <vscale x 16 x i8> @vmul_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) { 149; CHECK-LABEL: vmul_vv_nxv16i8: 150; CHECK: # %bb.0: 151; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 152; CHECK-NEXT: vmul.vv v8, v8, v10 153; CHECK-NEXT: ret 154 %vc = mul <vscale x 16 x i8> %va, %vb 155 ret <vscale x 16 x i8> %vc 156} 157 158define <vscale x 16 x i8> @vmul_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) { 159; CHECK-LABEL: vmul_vx_nxv16i8: 160; CHECK: # %bb.0: 161; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 162; CHECK-NEXT: vmul.vx v8, v8, a0 163; CHECK-NEXT: ret 164 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0 165 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer 166 %vc = mul <vscale x 16 x i8> %va, %splat 167 ret <vscale x 16 x i8> %vc 168} 169 170define <vscale x 16 x i8> @vmul_vi_nxv16i8_0(<vscale x 16 x i8> %va) { 171; CHECK-LABEL: vmul_vi_nxv16i8_0: 172; CHECK: # %bb.0: 173; CHECK-NEXT: li a0, -7 174; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 175; CHECK-NEXT: vmul.vx v8, v8, a0 176; CHECK-NEXT: ret 177 %head = insertelement <vscale x 16 x i8> poison, i8 -7, i32 0 178 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer 179 %vc = mul <vscale x 16 x i8> %va, %splat 180 ret <vscale x 16 x i8> %vc 181} 182 183define <vscale x 32 x i8> @vmul_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) { 184; CHECK-LABEL: vmul_vv_nxv32i8: 185; CHECK: # %bb.0: 186; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 187; CHECK-NEXT: vmul.vv v8, v8, v12 188; CHECK-NEXT: ret 189 %vc = mul <vscale x 32 x i8> %va, %vb 190 ret <vscale x 32 x i8> %vc 191} 192 193define <vscale x 32 x i8> @vmul_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) { 194; CHECK-LABEL: vmul_vx_nxv32i8: 195; CHECK: # %bb.0: 196; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 197; CHECK-NEXT: vmul.vx v8, v8, a0 198; CHECK-NEXT: ret 199 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0 200 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer 201 %vc = mul <vscale x 32 x i8> %va, %splat 202 ret <vscale x 32 x i8> %vc 203} 204 205define <vscale x 32 x i8> @vmul_vi_nxv32i8_0(<vscale x 32 x i8> %va) { 206; CHECK-LABEL: vmul_vi_nxv32i8_0: 207; CHECK: # %bb.0: 208; CHECK-NEXT: li a0, -7 209; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 210; CHECK-NEXT: vmul.vx v8, v8, a0 211; CHECK-NEXT: ret 212 %head = insertelement <vscale x 32 x i8> poison, i8 -7, i32 0 213 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer 214 %vc = mul <vscale x 32 x i8> %va, %splat 215 ret <vscale x 32 x i8> %vc 216} 217 218define <vscale x 64 x i8> @vmul_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) { 219; CHECK-LABEL: vmul_vv_nxv64i8: 220; CHECK: # %bb.0: 221; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 222; CHECK-NEXT: vmul.vv v8, v8, v16 223; CHECK-NEXT: ret 224 %vc = mul <vscale x 64 x i8> %va, %vb 225 ret <vscale x 64 x i8> %vc 226} 227 228define <vscale x 64 x i8> @vmul_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) { 229; CHECK-LABEL: vmul_vx_nxv64i8: 230; CHECK: # %bb.0: 231; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 232; CHECK-NEXT: vmul.vx v8, v8, a0 233; CHECK-NEXT: ret 234 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0 235 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer 236 %vc = mul <vscale x 64 x i8> %va, %splat 237 ret <vscale x 64 x i8> %vc 238} 239 240define <vscale x 64 x i8> @vmul_vi_nxv64i8_0(<vscale x 64 x i8> %va) { 241; CHECK-LABEL: vmul_vi_nxv64i8_0: 242; CHECK: # %bb.0: 243; CHECK-NEXT: li a0, -7 244; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 245; CHECK-NEXT: vmul.vx v8, v8, a0 246; CHECK-NEXT: ret 247 %head = insertelement <vscale x 64 x i8> poison, i8 -7, i32 0 248 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer 249 %vc = mul <vscale x 64 x i8> %va, %splat 250 ret <vscale x 64 x i8> %vc 251} 252 253define <vscale x 1 x i16> @vmul_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) { 254; CHECK-LABEL: vmul_vv_nxv1i16: 255; CHECK: # %bb.0: 256; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu 257; CHECK-NEXT: vmul.vv v8, v8, v9 258; CHECK-NEXT: ret 259 %vc = mul <vscale x 1 x i16> %va, %vb 260 ret <vscale x 1 x i16> %vc 261} 262 263define <vscale x 1 x i16> @vmul_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) { 264; CHECK-LABEL: vmul_vx_nxv1i16: 265; CHECK: # %bb.0: 266; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 267; CHECK-NEXT: vmul.vx v8, v8, a0 268; CHECK-NEXT: ret 269 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0 270 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer 271 %vc = mul <vscale x 1 x i16> %va, %splat 272 ret <vscale x 1 x i16> %vc 273} 274 275define <vscale x 1 x i16> @vmul_vi_nxv1i16_0(<vscale x 1 x i16> %va) { 276; CHECK-LABEL: vmul_vi_nxv1i16_0: 277; CHECK: # %bb.0: 278; CHECK-NEXT: li a0, -7 279; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 280; CHECK-NEXT: vmul.vx v8, v8, a0 281; CHECK-NEXT: ret 282 %head = insertelement <vscale x 1 x i16> poison, i16 -7, i32 0 283 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer 284 %vc = mul <vscale x 1 x i16> %va, %splat 285 ret <vscale x 1 x i16> %vc 286} 287 288define <vscale x 2 x i16> @vmul_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) { 289; CHECK-LABEL: vmul_vv_nxv2i16: 290; CHECK: # %bb.0: 291; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu 292; CHECK-NEXT: vmul.vv v8, v8, v9 293; CHECK-NEXT: ret 294 %vc = mul <vscale x 2 x i16> %va, %vb 295 ret <vscale x 2 x i16> %vc 296} 297 298define <vscale x 2 x i16> @vmul_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) { 299; CHECK-LABEL: vmul_vx_nxv2i16: 300; CHECK: # %bb.0: 301; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 302; CHECK-NEXT: vmul.vx v8, v8, a0 303; CHECK-NEXT: ret 304 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 305 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer 306 %vc = mul <vscale x 2 x i16> %va, %splat 307 ret <vscale x 2 x i16> %vc 308} 309 310define <vscale x 2 x i16> @vmul_vi_nxv2i16_0(<vscale x 2 x i16> %va) { 311; CHECK-LABEL: vmul_vi_nxv2i16_0: 312; CHECK: # %bb.0: 313; CHECK-NEXT: li a0, -7 314; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 315; CHECK-NEXT: vmul.vx v8, v8, a0 316; CHECK-NEXT: ret 317 %head = insertelement <vscale x 2 x i16> poison, i16 -7, i32 0 318 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer 319 %vc = mul <vscale x 2 x i16> %va, %splat 320 ret <vscale x 2 x i16> %vc 321} 322 323define <vscale x 4 x i16> @vmul_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) { 324; CHECK-LABEL: vmul_vv_nxv4i16: 325; CHECK: # %bb.0: 326; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 327; CHECK-NEXT: vmul.vv v8, v8, v9 328; CHECK-NEXT: ret 329 %vc = mul <vscale x 4 x i16> %va, %vb 330 ret <vscale x 4 x i16> %vc 331} 332 333define <vscale x 4 x i16> @vmul_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) { 334; CHECK-LABEL: vmul_vx_nxv4i16: 335; CHECK: # %bb.0: 336; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu 337; CHECK-NEXT: vmul.vx v8, v8, a0 338; CHECK-NEXT: ret 339 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0 340 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer 341 %vc = mul <vscale x 4 x i16> %va, %splat 342 ret <vscale x 4 x i16> %vc 343} 344 345define <vscale x 4 x i16> @vmul_vi_nxv4i16_0(<vscale x 4 x i16> %va) { 346; CHECK-LABEL: vmul_vi_nxv4i16_0: 347; CHECK: # %bb.0: 348; CHECK-NEXT: li a0, -7 349; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu 350; CHECK-NEXT: vmul.vx v8, v8, a0 351; CHECK-NEXT: ret 352 %head = insertelement <vscale x 4 x i16> poison, i16 -7, i32 0 353 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer 354 %vc = mul <vscale x 4 x i16> %va, %splat 355 ret <vscale x 4 x i16> %vc 356} 357 358define <vscale x 8 x i16> @vmul_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 359; CHECK-LABEL: vmul_vv_nxv8i16: 360; CHECK: # %bb.0: 361; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu 362; CHECK-NEXT: vmul.vv v8, v8, v10 363; CHECK-NEXT: ret 364 %vc = mul <vscale x 8 x i16> %va, %vb 365 ret <vscale x 8 x i16> %vc 366} 367 368define <vscale x 8 x i16> @vmul_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) { 369; CHECK-LABEL: vmul_vx_nxv8i16: 370; CHECK: # %bb.0: 371; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu 372; CHECK-NEXT: vmul.vx v8, v8, a0 373; CHECK-NEXT: ret 374 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 375 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 376 %vc = mul <vscale x 8 x i16> %va, %splat 377 ret <vscale x 8 x i16> %vc 378} 379 380define <vscale x 8 x i16> @vmul_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 381; CHECK-LABEL: vmul_vi_nxv8i16_0: 382; CHECK: # %bb.0: 383; CHECK-NEXT: li a0, -7 384; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu 385; CHECK-NEXT: vmul.vx v8, v8, a0 386; CHECK-NEXT: ret 387 %head = insertelement <vscale x 8 x i16> poison, i16 -7, i32 0 388 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 389 %vc = mul <vscale x 8 x i16> %va, %splat 390 ret <vscale x 8 x i16> %vc 391} 392 393define <vscale x 16 x i16> @vmul_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) { 394; CHECK-LABEL: vmul_vv_nxv16i16: 395; CHECK: # %bb.0: 396; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 397; CHECK-NEXT: vmul.vv v8, v8, v12 398; CHECK-NEXT: ret 399 %vc = mul <vscale x 16 x i16> %va, %vb 400 ret <vscale x 16 x i16> %vc 401} 402 403define <vscale x 16 x i16> @vmul_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) { 404; CHECK-LABEL: vmul_vx_nxv16i16: 405; CHECK: # %bb.0: 406; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu 407; CHECK-NEXT: vmul.vx v8, v8, a0 408; CHECK-NEXT: ret 409 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0 410 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 411 %vc = mul <vscale x 16 x i16> %va, %splat 412 ret <vscale x 16 x i16> %vc 413} 414 415define <vscale x 16 x i16> @vmul_vi_nxv16i16_0(<vscale x 16 x i16> %va) { 416; CHECK-LABEL: vmul_vi_nxv16i16_0: 417; CHECK: # %bb.0: 418; CHECK-NEXT: li a0, -7 419; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu 420; CHECK-NEXT: vmul.vx v8, v8, a0 421; CHECK-NEXT: ret 422 %head = insertelement <vscale x 16 x i16> poison, i16 -7, i32 0 423 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 424 %vc = mul <vscale x 16 x i16> %va, %splat 425 ret <vscale x 16 x i16> %vc 426} 427 428define <vscale x 32 x i16> @vmul_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) { 429; CHECK-LABEL: vmul_vv_nxv32i16: 430; CHECK: # %bb.0: 431; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu 432; CHECK-NEXT: vmul.vv v8, v8, v16 433; CHECK-NEXT: ret 434 %vc = mul <vscale x 32 x i16> %va, %vb 435 ret <vscale x 32 x i16> %vc 436} 437 438define <vscale x 32 x i16> @vmul_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) { 439; CHECK-LABEL: vmul_vx_nxv32i16: 440; CHECK: # %bb.0: 441; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu 442; CHECK-NEXT: vmul.vx v8, v8, a0 443; CHECK-NEXT: ret 444 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0 445 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer 446 %vc = mul <vscale x 32 x i16> %va, %splat 447 ret <vscale x 32 x i16> %vc 448} 449 450define <vscale x 32 x i16> @vmul_vi_nxv32i16_0(<vscale x 32 x i16> %va) { 451; CHECK-LABEL: vmul_vi_nxv32i16_0: 452; CHECK: # %bb.0: 453; CHECK-NEXT: li a0, -7 454; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu 455; CHECK-NEXT: vmul.vx v8, v8, a0 456; CHECK-NEXT: ret 457 %head = insertelement <vscale x 32 x i16> poison, i16 -7, i32 0 458 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer 459 %vc = mul <vscale x 32 x i16> %va, %splat 460 ret <vscale x 32 x i16> %vc 461} 462 463define <vscale x 1 x i32> @vmul_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) { 464; CHECK-LABEL: vmul_vv_nxv1i32: 465; CHECK: # %bb.0: 466; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu 467; CHECK-NEXT: vmul.vv v8, v8, v9 468; CHECK-NEXT: ret 469 %vc = mul <vscale x 1 x i32> %va, %vb 470 ret <vscale x 1 x i32> %vc 471} 472 473define <vscale x 1 x i32> @vmul_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) { 474; CHECK-LABEL: vmul_vx_nxv1i32: 475; CHECK: # %bb.0: 476; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 477; CHECK-NEXT: vmul.vx v8, v8, a0 478; CHECK-NEXT: ret 479 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 480 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer 481 %vc = mul <vscale x 1 x i32> %va, %splat 482 ret <vscale x 1 x i32> %vc 483} 484 485define <vscale x 1 x i32> @vmul_vi_nxv1i32_0(<vscale x 1 x i32> %va) { 486; CHECK-LABEL: vmul_vi_nxv1i32_0: 487; CHECK: # %bb.0: 488; CHECK-NEXT: li a0, -7 489; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 490; CHECK-NEXT: vmul.vx v8, v8, a0 491; CHECK-NEXT: ret 492 %head = insertelement <vscale x 1 x i32> poison, i32 -7, i32 0 493 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer 494 %vc = mul <vscale x 1 x i32> %va, %splat 495 ret <vscale x 1 x i32> %vc 496} 497 498define <vscale x 2 x i32> @vmul_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) { 499; CHECK-LABEL: vmul_vv_nxv2i32: 500; CHECK: # %bb.0: 501; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 502; CHECK-NEXT: vmul.vv v8, v8, v9 503; CHECK-NEXT: ret 504 %vc = mul <vscale x 2 x i32> %va, %vb 505 ret <vscale x 2 x i32> %vc 506} 507 508define <vscale x 2 x i32> @vmul_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) { 509; CHECK-LABEL: vmul_vx_nxv2i32: 510; CHECK: # %bb.0: 511; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu 512; CHECK-NEXT: vmul.vx v8, v8, a0 513; CHECK-NEXT: ret 514 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 515 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 516 %vc = mul <vscale x 2 x i32> %va, %splat 517 ret <vscale x 2 x i32> %vc 518} 519 520define <vscale x 2 x i32> @vmul_vi_nxv2i32_0(<vscale x 2 x i32> %va) { 521; CHECK-LABEL: vmul_vi_nxv2i32_0: 522; CHECK: # %bb.0: 523; CHECK-NEXT: li a0, -7 524; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu 525; CHECK-NEXT: vmul.vx v8, v8, a0 526; CHECK-NEXT: ret 527 %head = insertelement <vscale x 2 x i32> poison, i32 -7, i32 0 528 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 529 %vc = mul <vscale x 2 x i32> %va, %splat 530 ret <vscale x 2 x i32> %vc 531} 532 533define <vscale x 4 x i32> @vmul_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) { 534; CHECK-LABEL: vmul_vv_nxv4i32: 535; CHECK: # %bb.0: 536; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 537; CHECK-NEXT: vmul.vv v8, v8, v10 538; CHECK-NEXT: ret 539 %vc = mul <vscale x 4 x i32> %va, %vb 540 ret <vscale x 4 x i32> %vc 541} 542 543define <vscale x 4 x i32> @vmul_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) { 544; CHECK-LABEL: vmul_vx_nxv4i32: 545; CHECK: # %bb.0: 546; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu 547; CHECK-NEXT: vmul.vx v8, v8, a0 548; CHECK-NEXT: ret 549 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 550 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 551 %vc = mul <vscale x 4 x i32> %va, %splat 552 ret <vscale x 4 x i32> %vc 553} 554 555define <vscale x 4 x i32> @vmul_vi_nxv4i32_0(<vscale x 4 x i32> %va) { 556; CHECK-LABEL: vmul_vi_nxv4i32_0: 557; CHECK: # %bb.0: 558; CHECK-NEXT: li a0, -7 559; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu 560; CHECK-NEXT: vmul.vx v8, v8, a0 561; CHECK-NEXT: ret 562 %head = insertelement <vscale x 4 x i32> poison, i32 -7, i32 0 563 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 564 %vc = mul <vscale x 4 x i32> %va, %splat 565 ret <vscale x 4 x i32> %vc 566} 567 568define <vscale x 8 x i32> @vmul_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 569; CHECK-LABEL: vmul_vv_nxv8i32: 570; CHECK: # %bb.0: 571; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu 572; CHECK-NEXT: vmul.vv v8, v8, v12 573; CHECK-NEXT: ret 574 %vc = mul <vscale x 8 x i32> %va, %vb 575 ret <vscale x 8 x i32> %vc 576} 577 578define <vscale x 8 x i32> @vmul_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) { 579; CHECK-LABEL: vmul_vx_nxv8i32: 580; CHECK: # %bb.0: 581; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu 582; CHECK-NEXT: vmul.vx v8, v8, a0 583; CHECK-NEXT: ret 584 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 585 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 586 %vc = mul <vscale x 8 x i32> %va, %splat 587 ret <vscale x 8 x i32> %vc 588} 589 590define <vscale x 8 x i32> @vmul_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 591; CHECK-LABEL: vmul_vi_nxv8i32_0: 592; CHECK: # %bb.0: 593; CHECK-NEXT: li a0, -7 594; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu 595; CHECK-NEXT: vmul.vx v8, v8, a0 596; CHECK-NEXT: ret 597 %head = insertelement <vscale x 8 x i32> poison, i32 -7, i32 0 598 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 599 %vc = mul <vscale x 8 x i32> %va, %splat 600 ret <vscale x 8 x i32> %vc 601} 602 603define <vscale x 16 x i32> @vmul_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) { 604; CHECK-LABEL: vmul_vv_nxv16i32: 605; CHECK: # %bb.0: 606; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 607; CHECK-NEXT: vmul.vv v8, v8, v16 608; CHECK-NEXT: ret 609 %vc = mul <vscale x 16 x i32> %va, %vb 610 ret <vscale x 16 x i32> %vc 611} 612 613define <vscale x 16 x i32> @vmul_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) { 614; CHECK-LABEL: vmul_vx_nxv16i32: 615; CHECK: # %bb.0: 616; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu 617; CHECK-NEXT: vmul.vx v8, v8, a0 618; CHECK-NEXT: ret 619 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0 620 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 621 %vc = mul <vscale x 16 x i32> %va, %splat 622 ret <vscale x 16 x i32> %vc 623} 624 625define <vscale x 16 x i32> @vmul_vi_nxv16i32_0(<vscale x 16 x i32> %va) { 626; CHECK-LABEL: vmul_vi_nxv16i32_0: 627; CHECK: # %bb.0: 628; CHECK-NEXT: li a0, -7 629; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu 630; CHECK-NEXT: vmul.vx v8, v8, a0 631; CHECK-NEXT: ret 632 %head = insertelement <vscale x 16 x i32> poison, i32 -7, i32 0 633 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 634 %vc = mul <vscale x 16 x i32> %va, %splat 635 ret <vscale x 16 x i32> %vc 636} 637 638define <vscale x 1 x i64> @vmul_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) { 639; CHECK-LABEL: vmul_vv_nxv1i64: 640; CHECK: # %bb.0: 641; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 642; CHECK-NEXT: vmul.vv v8, v8, v9 643; CHECK-NEXT: ret 644 %vc = mul <vscale x 1 x i64> %va, %vb 645 ret <vscale x 1 x i64> %vc 646} 647 648define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { 649; RV32-LABEL: vmul_vx_nxv1i64: 650; RV32: # %bb.0: 651; RV32-NEXT: addi sp, sp, -16 652; RV32-NEXT: .cfi_def_cfa_offset 16 653; RV32-NEXT: sw a1, 12(sp) 654; RV32-NEXT: sw a0, 8(sp) 655; RV32-NEXT: addi a0, sp, 8 656; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu 657; RV32-NEXT: vlse64.v v9, (a0), zero 658; RV32-NEXT: vmul.vv v8, v8, v9 659; RV32-NEXT: addi sp, sp, 16 660; RV32-NEXT: ret 661; 662; RV64-LABEL: vmul_vx_nxv1i64: 663; RV64: # %bb.0: 664; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu 665; RV64-NEXT: vmul.vx v8, v8, a0 666; RV64-NEXT: ret 667 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 668 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 669 %vc = mul <vscale x 1 x i64> %va, %splat 670 ret <vscale x 1 x i64> %vc 671} 672 673define <vscale x 1 x i64> @vmul_vi_nxv1i64_0(<vscale x 1 x i64> %va) { 674; CHECK-LABEL: vmul_vi_nxv1i64_0: 675; CHECK: # %bb.0: 676; CHECK-NEXT: li a0, -7 677; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu 678; CHECK-NEXT: vmul.vx v8, v8, a0 679; CHECK-NEXT: ret 680 %head = insertelement <vscale x 1 x i64> poison, i64 -7, i32 0 681 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 682 %vc = mul <vscale x 1 x i64> %va, %splat 683 ret <vscale x 1 x i64> %vc 684} 685 686define <vscale x 1 x i64> @vmul_vi_nxv1i64_1(<vscale x 1 x i64> %va) { 687; CHECK-LABEL: vmul_vi_nxv1i64_1: 688; CHECK: # %bb.0: 689; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 690; CHECK-NEXT: vadd.vv v8, v8, v8 691; CHECK-NEXT: ret 692 %head = insertelement <vscale x 1 x i64> poison, i64 2, i32 0 693 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 694 %vc = mul <vscale x 1 x i64> %va, %splat 695 ret <vscale x 1 x i64> %vc 696} 697 698define <vscale x 1 x i64> @vmul_vi_nxv1i64_2(<vscale x 1 x i64> %va) { 699; CHECK-LABEL: vmul_vi_nxv1i64_2: 700; CHECK: # %bb.0: 701; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 702; CHECK-NEXT: vsll.vi v8, v8, 4 703; CHECK-NEXT: ret 704 %head = insertelement <vscale x 1 x i64> poison, i64 16, i32 0 705 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 706 %vc = mul <vscale x 1 x i64> %va, %splat 707 ret <vscale x 1 x i64> %vc 708} 709 710define <vscale x 2 x i64> @vmul_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) { 711; CHECK-LABEL: vmul_vv_nxv2i64: 712; CHECK: # %bb.0: 713; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 714; CHECK-NEXT: vmul.vv v8, v8, v10 715; CHECK-NEXT: ret 716 %vc = mul <vscale x 2 x i64> %va, %vb 717 ret <vscale x 2 x i64> %vc 718} 719 720define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { 721; RV32-LABEL: vmul_vx_nxv2i64: 722; RV32: # %bb.0: 723; RV32-NEXT: addi sp, sp, -16 724; RV32-NEXT: .cfi_def_cfa_offset 16 725; RV32-NEXT: sw a1, 12(sp) 726; RV32-NEXT: sw a0, 8(sp) 727; RV32-NEXT: addi a0, sp, 8 728; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu 729; RV32-NEXT: vlse64.v v10, (a0), zero 730; RV32-NEXT: vmul.vv v8, v8, v10 731; RV32-NEXT: addi sp, sp, 16 732; RV32-NEXT: ret 733; 734; RV64-LABEL: vmul_vx_nxv2i64: 735; RV64: # %bb.0: 736; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu 737; RV64-NEXT: vmul.vx v8, v8, a0 738; RV64-NEXT: ret 739 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 740 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 741 %vc = mul <vscale x 2 x i64> %va, %splat 742 ret <vscale x 2 x i64> %vc 743} 744 745define <vscale x 2 x i64> @vmul_vi_nxv2i64_0(<vscale x 2 x i64> %va) { 746; CHECK-LABEL: vmul_vi_nxv2i64_0: 747; CHECK: # %bb.0: 748; CHECK-NEXT: li a0, -7 749; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu 750; CHECK-NEXT: vmul.vx v8, v8, a0 751; CHECK-NEXT: ret 752 %head = insertelement <vscale x 2 x i64> poison, i64 -7, i32 0 753 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 754 %vc = mul <vscale x 2 x i64> %va, %splat 755 ret <vscale x 2 x i64> %vc 756} 757 758define <vscale x 2 x i64> @vmul_vi_nxv2i64_1(<vscale x 2 x i64> %va) { 759; CHECK-LABEL: vmul_vi_nxv2i64_1: 760; CHECK: # %bb.0: 761; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 762; CHECK-NEXT: vadd.vv v8, v8, v8 763; CHECK-NEXT: ret 764 %head = insertelement <vscale x 2 x i64> poison, i64 2, i32 0 765 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 766 %vc = mul <vscale x 2 x i64> %va, %splat 767 ret <vscale x 2 x i64> %vc 768} 769 770define <vscale x 2 x i64> @vmul_vi_nxv2i64_2(<vscale x 2 x i64> %va) { 771; CHECK-LABEL: vmul_vi_nxv2i64_2: 772; CHECK: # %bb.0: 773; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 774; CHECK-NEXT: vsll.vi v8, v8, 4 775; CHECK-NEXT: ret 776 %head = insertelement <vscale x 2 x i64> poison, i64 16, i32 0 777 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 778 %vc = mul <vscale x 2 x i64> %va, %splat 779 ret <vscale x 2 x i64> %vc 780} 781 782define <vscale x 4 x i64> @vmul_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) { 783; CHECK-LABEL: vmul_vv_nxv4i64: 784; CHECK: # %bb.0: 785; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 786; CHECK-NEXT: vmul.vv v8, v8, v12 787; CHECK-NEXT: ret 788 %vc = mul <vscale x 4 x i64> %va, %vb 789 ret <vscale x 4 x i64> %vc 790} 791 792define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { 793; RV32-LABEL: vmul_vx_nxv4i64: 794; RV32: # %bb.0: 795; RV32-NEXT: addi sp, sp, -16 796; RV32-NEXT: .cfi_def_cfa_offset 16 797; RV32-NEXT: sw a1, 12(sp) 798; RV32-NEXT: sw a0, 8(sp) 799; RV32-NEXT: addi a0, sp, 8 800; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu 801; RV32-NEXT: vlse64.v v12, (a0), zero 802; RV32-NEXT: vmul.vv v8, v8, v12 803; RV32-NEXT: addi sp, sp, 16 804; RV32-NEXT: ret 805; 806; RV64-LABEL: vmul_vx_nxv4i64: 807; RV64: # %bb.0: 808; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu 809; RV64-NEXT: vmul.vx v8, v8, a0 810; RV64-NEXT: ret 811 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 812 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 813 %vc = mul <vscale x 4 x i64> %va, %splat 814 ret <vscale x 4 x i64> %vc 815} 816 817define <vscale x 4 x i64> @vmul_vi_nxv4i64_0(<vscale x 4 x i64> %va) { 818; CHECK-LABEL: vmul_vi_nxv4i64_0: 819; CHECK: # %bb.0: 820; CHECK-NEXT: li a0, -7 821; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu 822; CHECK-NEXT: vmul.vx v8, v8, a0 823; CHECK-NEXT: ret 824 %head = insertelement <vscale x 4 x i64> poison, i64 -7, i32 0 825 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 826 %vc = mul <vscale x 4 x i64> %va, %splat 827 ret <vscale x 4 x i64> %vc 828} 829 830define <vscale x 4 x i64> @vmul_vi_nxv4i64_1(<vscale x 4 x i64> %va) { 831; CHECK-LABEL: vmul_vi_nxv4i64_1: 832; CHECK: # %bb.0: 833; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 834; CHECK-NEXT: vadd.vv v8, v8, v8 835; CHECK-NEXT: ret 836 %head = insertelement <vscale x 4 x i64> poison, i64 2, i32 0 837 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 838 %vc = mul <vscale x 4 x i64> %va, %splat 839 ret <vscale x 4 x i64> %vc 840} 841 842define <vscale x 4 x i64> @vmul_vi_nxv4i64_2(<vscale x 4 x i64> %va) { 843; CHECK-LABEL: vmul_vi_nxv4i64_2: 844; CHECK: # %bb.0: 845; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 846; CHECK-NEXT: vsll.vi v8, v8, 4 847; CHECK-NEXT: ret 848 %head = insertelement <vscale x 4 x i64> poison, i64 16, i32 0 849 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 850 %vc = mul <vscale x 4 x i64> %va, %splat 851 ret <vscale x 4 x i64> %vc 852} 853 854define <vscale x 8 x i64> @vmul_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 855; CHECK-LABEL: vmul_vv_nxv8i64: 856; CHECK: # %bb.0: 857; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 858; CHECK-NEXT: vmul.vv v8, v8, v16 859; CHECK-NEXT: ret 860 %vc = mul <vscale x 8 x i64> %va, %vb 861 ret <vscale x 8 x i64> %vc 862} 863 864define <vscale x 8 x i64> @vmul_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 865; RV32-LABEL: vmul_vx_nxv8i64: 866; RV32: # %bb.0: 867; RV32-NEXT: addi sp, sp, -16 868; RV32-NEXT: .cfi_def_cfa_offset 16 869; RV32-NEXT: sw a1, 12(sp) 870; RV32-NEXT: sw a0, 8(sp) 871; RV32-NEXT: addi a0, sp, 8 872; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu 873; RV32-NEXT: vlse64.v v16, (a0), zero 874; RV32-NEXT: vmul.vv v8, v8, v16 875; RV32-NEXT: addi sp, sp, 16 876; RV32-NEXT: ret 877; 878; RV64-LABEL: vmul_vx_nxv8i64: 879; RV64: # %bb.0: 880; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 881; RV64-NEXT: vmul.vx v8, v8, a0 882; RV64-NEXT: ret 883 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 884 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 885 %vc = mul <vscale x 8 x i64> %va, %splat 886 ret <vscale x 8 x i64> %vc 887} 888 889define <vscale x 8 x i64> @vmul_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 890; CHECK-LABEL: vmul_vi_nxv8i64_0: 891; CHECK: # %bb.0: 892; CHECK-NEXT: li a0, -7 893; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu 894; CHECK-NEXT: vmul.vx v8, v8, a0 895; CHECK-NEXT: ret 896 %head = insertelement <vscale x 8 x i64> poison, i64 -7, i32 0 897 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 898 %vc = mul <vscale x 8 x i64> %va, %splat 899 ret <vscale x 8 x i64> %vc 900} 901 902define <vscale x 8 x i64> @vmul_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 903; CHECK-LABEL: vmul_vi_nxv8i64_1: 904; CHECK: # %bb.0: 905; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 906; CHECK-NEXT: vadd.vv v8, v8, v8 907; CHECK-NEXT: ret 908 %head = insertelement <vscale x 8 x i64> poison, i64 2, i32 0 909 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 910 %vc = mul <vscale x 8 x i64> %va, %splat 911 ret <vscale x 8 x i64> %vc 912} 913 914define <vscale x 8 x i64> @vmul_vi_nxv8i64_2(<vscale x 8 x i64> %va) { 915; CHECK-LABEL: vmul_vi_nxv8i64_2: 916; CHECK: # %bb.0: 917; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 918; CHECK-NEXT: vsll.vi v8, v8, 4 919; CHECK-NEXT: ret 920 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 921 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 922 %vc = mul <vscale x 8 x i64> %va, %splat 923 ret <vscale x 8 x i64> %vc 924} 925 926define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind { 927; RV32-LABEL: vmul_xx_nxv8i64: 928; RV32: # %bb.0: 929; RV32-NEXT: addi sp, sp, -16 930; RV32-NEXT: sw a1, 12(sp) 931; RV32-NEXT: sw a0, 8(sp) 932; RV32-NEXT: addi a0, sp, 8 933; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu 934; RV32-NEXT: vlse64.v v8, (a0), zero 935; RV32-NEXT: sw a3, 12(sp) 936; RV32-NEXT: sw a2, 8(sp) 937; RV32-NEXT: vlse64.v v16, (a0), zero 938; RV32-NEXT: vmul.vv v8, v8, v16 939; RV32-NEXT: addi sp, sp, 16 940; RV32-NEXT: ret 941; 942; RV64NOM-LABEL: vmul_xx_nxv8i64: 943; RV64NOM: # %bb.0: 944; RV64NOM-NEXT: vsetvli a2, zero, e64, m8, ta, mu 945; RV64NOM-NEXT: vmv.v.x v8, a0 946; RV64NOM-NEXT: vmul.vx v8, v8, a1 947; RV64NOM-NEXT: ret 948; 949; RV64M-LABEL: vmul_xx_nxv8i64: 950; RV64M: # %bb.0: 951; RV64M-NEXT: mul a0, a0, a1 952; RV64M-NEXT: vsetvli a1, zero, e64, m8, ta, mu 953; RV64M-NEXT: vmv.v.x v8, a0 954; RV64M-NEXT: ret 955 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0 956 %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 957 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 958 %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 959 %v = mul <vscale x 8 x i64> %splat1, %splat2 960 ret <vscale x 8 x i64> %v 961} 962