History log of /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll (Results 1 – 6 of 6)
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# bbd2ecf9 17-Mar-2022 Craig Topper <[email protected]>

[RISCV] Add +experimental-zvfh extension to cover half types in vectors.

Currently we allow half types in vectors if the scalar Zfh extension
is enabled. This behavior is not inline with the vector

[RISCV] Add +experimental-zvfh extension to cover half types in vectors.

Currently we allow half types in vectors if the scalar Zfh extension
is enabled. This behavior is not inline with the vector spec. For f32
and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly control
the availablity of floating point types in vectors.

In order to make our compiler compliant, we either need to remove all support
for half in vectors or we need an extension to control it.

Draft spec here https://github.com/riscv/riscv-v-spec/pull/780

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D121345

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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init
# e9ceeedf 01-Feb-2022 Fraser Cormack <[email protected]>

[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests


# 3cf15af2 21-Jan-2022 eopXD <[email protected]>

[RISCV] Remove experimental prefix from rvv-related extensions.

Extensions affected: +v, +zve*, +zvl*

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117860


Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3
# a0a76fee 15-Jan-2022 Shao-Ce SUN <[email protected]>

[RISCV] update zfh and zfhmin extention to v1.0

`zfh` and `zfhmin` have been ratified, with version 1.0.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117098


Revision tags: llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2
# 242ddd50 08-Jun-2021 Jim Lin <[email protected]>

[RISCV][NFC] Add a single space after comma for VType

In most of cases, it has a single space after comma in assembly operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llv

[RISCV][NFC] Add a single space after comma for VType

In most of cases, it has a single space after comma in assembly operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103790

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Revision tags: llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3
# ad5307aa 30-Jan-2021 Craig Topper <[email protected]>

[RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines.

The IR and CHECK lines are identical so just keep one copy.