1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
4
5define <vscale x 1 x i8> @vsra_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
6; CHECK-LABEL: vsra_vv_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
9; CHECK-NEXT:    vsra.vv v8, v8, v9
10; CHECK-NEXT:    ret
11  %vc = ashr <vscale x 1 x i8> %va, %vb
12  ret <vscale x 1 x i8> %vc
13}
14
15define <vscale x 1 x i8> @vsra_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
16; CHECK-LABEL: vsra_vx_nxv1i8:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
19; CHECK-NEXT:    vsra.vx v8, v8, a0
20; CHECK-NEXT:    ret
21  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
22  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
23  %vc = ashr <vscale x 1 x i8> %va, %splat
24  ret <vscale x 1 x i8> %vc
25}
26
27define <vscale x 1 x i8> @vsra_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
28; CHECK-LABEL: vsra_vi_nxv1i8_0:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
31; CHECK-NEXT:    vsra.vi v8, v8, 6
32; CHECK-NEXT:    ret
33  %head = insertelement <vscale x 1 x i8> poison, i8 6, i32 0
34  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
35  %vc = ashr <vscale x 1 x i8> %va, %splat
36  ret <vscale x 1 x i8> %vc
37}
38
39define <vscale x 2 x i8> @vsra_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
40; CHECK-LABEL: vsra_vv_nxv2i8:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
43; CHECK-NEXT:    vsra.vv v8, v8, v9
44; CHECK-NEXT:    ret
45  %vc = ashr <vscale x 2 x i8> %va, %vb
46  ret <vscale x 2 x i8> %vc
47}
48
49define <vscale x 2 x i8> @vsra_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
50; CHECK-LABEL: vsra_vx_nxv2i8:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
53; CHECK-NEXT:    vsra.vx v8, v8, a0
54; CHECK-NEXT:    ret
55  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
56  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
57  %vc = ashr <vscale x 2 x i8> %va, %splat
58  ret <vscale x 2 x i8> %vc
59}
60
61define <vscale x 2 x i8> @vsra_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
62; CHECK-LABEL: vsra_vi_nxv2i8_0:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
65; CHECK-NEXT:    vsra.vi v8, v8, 6
66; CHECK-NEXT:    ret
67  %head = insertelement <vscale x 2 x i8> poison, i8 6, i32 0
68  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
69  %vc = ashr <vscale x 2 x i8> %va, %splat
70  ret <vscale x 2 x i8> %vc
71}
72
73define <vscale x 4 x i8> @vsra_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
74; CHECK-LABEL: vsra_vv_nxv4i8:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
77; CHECK-NEXT:    vsra.vv v8, v8, v9
78; CHECK-NEXT:    ret
79  %vc = ashr <vscale x 4 x i8> %va, %vb
80  ret <vscale x 4 x i8> %vc
81}
82
83define <vscale x 4 x i8> @vsra_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
84; CHECK-LABEL: vsra_vx_nxv4i8:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
87; CHECK-NEXT:    vsra.vx v8, v8, a0
88; CHECK-NEXT:    ret
89  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
90  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
91  %vc = ashr <vscale x 4 x i8> %va, %splat
92  ret <vscale x 4 x i8> %vc
93}
94
95define <vscale x 4 x i8> @vsra_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
96; CHECK-LABEL: vsra_vi_nxv4i8_0:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
99; CHECK-NEXT:    vsra.vi v8, v8, 6
100; CHECK-NEXT:    ret
101  %head = insertelement <vscale x 4 x i8> poison, i8 6, i32 0
102  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
103  %vc = ashr <vscale x 4 x i8> %va, %splat
104  ret <vscale x 4 x i8> %vc
105}
106
107define <vscale x 8 x i8> @vsra_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
108; CHECK-LABEL: vsra_vv_nxv8i8:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
111; CHECK-NEXT:    vsra.vv v8, v8, v9
112; CHECK-NEXT:    ret
113  %vc = ashr <vscale x 8 x i8> %va, %vb
114  ret <vscale x 8 x i8> %vc
115}
116
117define <vscale x 8 x i8> @vsra_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
118; CHECK-LABEL: vsra_vx_nxv8i8:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
121; CHECK-NEXT:    vsra.vx v8, v8, a0
122; CHECK-NEXT:    ret
123  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
124  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
125  %vc = ashr <vscale x 8 x i8> %va, %splat
126  ret <vscale x 8 x i8> %vc
127}
128
129define <vscale x 8 x i8> @vsra_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
130; CHECK-LABEL: vsra_vi_nxv8i8_0:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
133; CHECK-NEXT:    vsra.vi v8, v8, 6
134; CHECK-NEXT:    ret
135  %head = insertelement <vscale x 8 x i8> poison, i8 6, i32 0
136  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
137  %vc = ashr <vscale x 8 x i8> %va, %splat
138  ret <vscale x 8 x i8> %vc
139}
140
141define <vscale x 16 x i8> @vsra_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
142; CHECK-LABEL: vsra_vv_nxv16i8:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
145; CHECK-NEXT:    vsra.vv v8, v8, v10
146; CHECK-NEXT:    ret
147  %vc = ashr <vscale x 16 x i8> %va, %vb
148  ret <vscale x 16 x i8> %vc
149}
150
151define <vscale x 16 x i8> @vsra_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
152; CHECK-LABEL: vsra_vx_nxv16i8:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
155; CHECK-NEXT:    vsra.vx v8, v8, a0
156; CHECK-NEXT:    ret
157  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
158  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
159  %vc = ashr <vscale x 16 x i8> %va, %splat
160  ret <vscale x 16 x i8> %vc
161}
162
163define <vscale x 16 x i8> @vsra_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
164; CHECK-LABEL: vsra_vi_nxv16i8_0:
165; CHECK:       # %bb.0:
166; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
167; CHECK-NEXT:    vsra.vi v8, v8, 6
168; CHECK-NEXT:    ret
169  %head = insertelement <vscale x 16 x i8> poison, i8 6, i32 0
170  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
171  %vc = ashr <vscale x 16 x i8> %va, %splat
172  ret <vscale x 16 x i8> %vc
173}
174
175define <vscale x 32 x i8> @vsra_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
176; CHECK-LABEL: vsra_vv_nxv32i8:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
179; CHECK-NEXT:    vsra.vv v8, v8, v12
180; CHECK-NEXT:    ret
181  %vc = ashr <vscale x 32 x i8> %va, %vb
182  ret <vscale x 32 x i8> %vc
183}
184
185define <vscale x 32 x i8> @vsra_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
186; CHECK-LABEL: vsra_vx_nxv32i8:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
189; CHECK-NEXT:    vsra.vx v8, v8, a0
190; CHECK-NEXT:    ret
191  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
192  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
193  %vc = ashr <vscale x 32 x i8> %va, %splat
194  ret <vscale x 32 x i8> %vc
195}
196
197define <vscale x 32 x i8> @vsra_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
198; CHECK-LABEL: vsra_vi_nxv32i8_0:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
201; CHECK-NEXT:    vsra.vi v8, v8, 6
202; CHECK-NEXT:    ret
203  %head = insertelement <vscale x 32 x i8> poison, i8 6, i32 0
204  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
205  %vc = ashr <vscale x 32 x i8> %va, %splat
206  ret <vscale x 32 x i8> %vc
207}
208
209define <vscale x 64 x i8> @vsra_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
210; CHECK-LABEL: vsra_vv_nxv64i8:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
213; CHECK-NEXT:    vsra.vv v8, v8, v16
214; CHECK-NEXT:    ret
215  %vc = ashr <vscale x 64 x i8> %va, %vb
216  ret <vscale x 64 x i8> %vc
217}
218
219define <vscale x 64 x i8> @vsra_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
220; CHECK-LABEL: vsra_vx_nxv64i8:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
223; CHECK-NEXT:    vsra.vx v8, v8, a0
224; CHECK-NEXT:    ret
225  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
226  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
227  %vc = ashr <vscale x 64 x i8> %va, %splat
228  ret <vscale x 64 x i8> %vc
229}
230
231define <vscale x 64 x i8> @vsra_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
232; CHECK-LABEL: vsra_vi_nxv64i8_0:
233; CHECK:       # %bb.0:
234; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
235; CHECK-NEXT:    vsra.vi v8, v8, 6
236; CHECK-NEXT:    ret
237  %head = insertelement <vscale x 64 x i8> poison, i8 6, i32 0
238  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
239  %vc = ashr <vscale x 64 x i8> %va, %splat
240  ret <vscale x 64 x i8> %vc
241}
242
243define <vscale x 1 x i16> @vsra_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
244; CHECK-LABEL: vsra_vv_nxv1i16:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
247; CHECK-NEXT:    vsra.vv v8, v8, v9
248; CHECK-NEXT:    ret
249  %vc = ashr <vscale x 1 x i16> %va, %vb
250  ret <vscale x 1 x i16> %vc
251}
252
253define <vscale x 1 x i16> @vsra_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
254; CHECK-LABEL: vsra_vx_nxv1i16:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
257; CHECK-NEXT:    vsra.vx v8, v8, a0
258; CHECK-NEXT:    ret
259  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
260  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
261  %vc = ashr <vscale x 1 x i16> %va, %splat
262  ret <vscale x 1 x i16> %vc
263}
264
265define <vscale x 1 x i16> @vsra_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
266; CHECK-LABEL: vsra_vi_nxv1i16_0:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
269; CHECK-NEXT:    vsra.vi v8, v8, 6
270; CHECK-NEXT:    ret
271  %head = insertelement <vscale x 1 x i16> poison, i16 6, i32 0
272  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
273  %vc = ashr <vscale x 1 x i16> %va, %splat
274  ret <vscale x 1 x i16> %vc
275}
276
277define <vscale x 2 x i16> @vsra_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
278; CHECK-LABEL: vsra_vv_nxv2i16:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
281; CHECK-NEXT:    vsra.vv v8, v8, v9
282; CHECK-NEXT:    ret
283  %vc = ashr <vscale x 2 x i16> %va, %vb
284  ret <vscale x 2 x i16> %vc
285}
286
287define <vscale x 2 x i16> @vsra_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
288; CHECK-LABEL: vsra_vx_nxv2i16:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
291; CHECK-NEXT:    vsra.vx v8, v8, a0
292; CHECK-NEXT:    ret
293  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
294  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
295  %vc = ashr <vscale x 2 x i16> %va, %splat
296  ret <vscale x 2 x i16> %vc
297}
298
299define <vscale x 2 x i16> @vsra_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
300; CHECK-LABEL: vsra_vi_nxv2i16_0:
301; CHECK:       # %bb.0:
302; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
303; CHECK-NEXT:    vsra.vi v8, v8, 6
304; CHECK-NEXT:    ret
305  %head = insertelement <vscale x 2 x i16> poison, i16 6, i32 0
306  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
307  %vc = ashr <vscale x 2 x i16> %va, %splat
308  ret <vscale x 2 x i16> %vc
309}
310
311define <vscale x 4 x i16> @vsra_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
312; CHECK-LABEL: vsra_vv_nxv4i16:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
315; CHECK-NEXT:    vsra.vv v8, v8, v9
316; CHECK-NEXT:    ret
317  %vc = ashr <vscale x 4 x i16> %va, %vb
318  ret <vscale x 4 x i16> %vc
319}
320
321define <vscale x 4 x i16> @vsra_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
322; CHECK-LABEL: vsra_vx_nxv4i16:
323; CHECK:       # %bb.0:
324; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
325; CHECK-NEXT:    vsra.vx v8, v8, a0
326; CHECK-NEXT:    ret
327  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
328  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
329  %vc = ashr <vscale x 4 x i16> %va, %splat
330  ret <vscale x 4 x i16> %vc
331}
332
333define <vscale x 4 x i16> @vsra_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
334; CHECK-LABEL: vsra_vi_nxv4i16_0:
335; CHECK:       # %bb.0:
336; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
337; CHECK-NEXT:    vsra.vi v8, v8, 6
338; CHECK-NEXT:    ret
339  %head = insertelement <vscale x 4 x i16> poison, i16 6, i32 0
340  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
341  %vc = ashr <vscale x 4 x i16> %va, %splat
342  ret <vscale x 4 x i16> %vc
343}
344
345define <vscale x 8 x i16> @vsra_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
346; CHECK-LABEL: vsra_vv_nxv8i16:
347; CHECK:       # %bb.0:
348; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
349; CHECK-NEXT:    vsra.vv v8, v8, v10
350; CHECK-NEXT:    ret
351  %vc = ashr <vscale x 8 x i16> %va, %vb
352  ret <vscale x 8 x i16> %vc
353}
354
355define <vscale x 8 x i16> @vsra_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
356; CHECK-LABEL: vsra_vx_nxv8i16:
357; CHECK:       # %bb.0:
358; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
359; CHECK-NEXT:    vsra.vx v8, v8, a0
360; CHECK-NEXT:    ret
361  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
362  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
363  %vc = ashr <vscale x 8 x i16> %va, %splat
364  ret <vscale x 8 x i16> %vc
365}
366
367define <vscale x 8 x i16> @vsra_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
368; CHECK-LABEL: vsra_vi_nxv8i16_0:
369; CHECK:       # %bb.0:
370; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
371; CHECK-NEXT:    vsra.vi v8, v8, 6
372; CHECK-NEXT:    ret
373  %head = insertelement <vscale x 8 x i16> poison, i16 6, i32 0
374  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
375  %vc = ashr <vscale x 8 x i16> %va, %splat
376  ret <vscale x 8 x i16> %vc
377}
378
379define <vscale x 16 x i16> @vsra_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
380; CHECK-LABEL: vsra_vv_nxv16i16:
381; CHECK:       # %bb.0:
382; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
383; CHECK-NEXT:    vsra.vv v8, v8, v12
384; CHECK-NEXT:    ret
385  %vc = ashr <vscale x 16 x i16> %va, %vb
386  ret <vscale x 16 x i16> %vc
387}
388
389define <vscale x 16 x i16> @vsra_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
390; CHECK-LABEL: vsra_vx_nxv16i16:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
393; CHECK-NEXT:    vsra.vx v8, v8, a0
394; CHECK-NEXT:    ret
395  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
396  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
397  %vc = ashr <vscale x 16 x i16> %va, %splat
398  ret <vscale x 16 x i16> %vc
399}
400
401define <vscale x 16 x i16> @vsra_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
402; CHECK-LABEL: vsra_vi_nxv16i16_0:
403; CHECK:       # %bb.0:
404; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
405; CHECK-NEXT:    vsra.vi v8, v8, 6
406; CHECK-NEXT:    ret
407  %head = insertelement <vscale x 16 x i16> poison, i16 6, i32 0
408  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
409  %vc = ashr <vscale x 16 x i16> %va, %splat
410  ret <vscale x 16 x i16> %vc
411}
412
413define <vscale x 32 x i16> @vsra_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
414; CHECK-LABEL: vsra_vv_nxv32i16:
415; CHECK:       # %bb.0:
416; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
417; CHECK-NEXT:    vsra.vv v8, v8, v16
418; CHECK-NEXT:    ret
419  %vc = ashr <vscale x 32 x i16> %va, %vb
420  ret <vscale x 32 x i16> %vc
421}
422
423define <vscale x 32 x i16> @vsra_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
424; CHECK-LABEL: vsra_vx_nxv32i16:
425; CHECK:       # %bb.0:
426; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
427; CHECK-NEXT:    vsra.vx v8, v8, a0
428; CHECK-NEXT:    ret
429  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
430  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
431  %vc = ashr <vscale x 32 x i16> %va, %splat
432  ret <vscale x 32 x i16> %vc
433}
434
435define <vscale x 32 x i16> @vsra_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
436; CHECK-LABEL: vsra_vi_nxv32i16_0:
437; CHECK:       # %bb.0:
438; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
439; CHECK-NEXT:    vsra.vi v8, v8, 6
440; CHECK-NEXT:    ret
441  %head = insertelement <vscale x 32 x i16> poison, i16 6, i32 0
442  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
443  %vc = ashr <vscale x 32 x i16> %va, %splat
444  ret <vscale x 32 x i16> %vc
445}
446
447define <vscale x 1 x i32> @vsra_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
448; CHECK-LABEL: vsra_vv_nxv1i32:
449; CHECK:       # %bb.0:
450; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
451; CHECK-NEXT:    vsra.vv v8, v8, v9
452; CHECK-NEXT:    ret
453  %vc = ashr <vscale x 1 x i32> %va, %vb
454  ret <vscale x 1 x i32> %vc
455}
456
457define <vscale x 1 x i32> @vsra_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
458; CHECK-LABEL: vsra_vx_nxv1i32:
459; CHECK:       # %bb.0:
460; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
461; CHECK-NEXT:    vsra.vx v8, v8, a0
462; CHECK-NEXT:    ret
463  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
464  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
465  %vc = ashr <vscale x 1 x i32> %va, %splat
466  ret <vscale x 1 x i32> %vc
467}
468
469define <vscale x 1 x i32> @vsra_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
470; CHECK-LABEL: vsra_vi_nxv1i32_0:
471; CHECK:       # %bb.0:
472; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
473; CHECK-NEXT:    vsra.vi v8, v8, 31
474; CHECK-NEXT:    ret
475  %head = insertelement <vscale x 1 x i32> poison, i32 31, i32 0
476  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
477  %vc = ashr <vscale x 1 x i32> %va, %splat
478  ret <vscale x 1 x i32> %vc
479}
480
481define <vscale x 2 x i32> @vsra_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
482; CHECK-LABEL: vsra_vv_nxv2i32:
483; CHECK:       # %bb.0:
484; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
485; CHECK-NEXT:    vsra.vv v8, v8, v9
486; CHECK-NEXT:    ret
487  %vc = ashr <vscale x 2 x i32> %va, %vb
488  ret <vscale x 2 x i32> %vc
489}
490
491define <vscale x 2 x i32> @vsra_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
492; CHECK-LABEL: vsra_vx_nxv2i32:
493; CHECK:       # %bb.0:
494; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
495; CHECK-NEXT:    vsra.vx v8, v8, a0
496; CHECK-NEXT:    ret
497  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
498  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
499  %vc = ashr <vscale x 2 x i32> %va, %splat
500  ret <vscale x 2 x i32> %vc
501}
502
503define <vscale x 2 x i32> @vsra_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
504; CHECK-LABEL: vsra_vi_nxv2i32_0:
505; CHECK:       # %bb.0:
506; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
507; CHECK-NEXT:    vsra.vi v8, v8, 31
508; CHECK-NEXT:    ret
509  %head = insertelement <vscale x 2 x i32> poison, i32 31, i32 0
510  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
511  %vc = ashr <vscale x 2 x i32> %va, %splat
512  ret <vscale x 2 x i32> %vc
513}
514
515define <vscale x 4 x i32> @vsra_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
516; CHECK-LABEL: vsra_vv_nxv4i32:
517; CHECK:       # %bb.0:
518; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
519; CHECK-NEXT:    vsra.vv v8, v8, v10
520; CHECK-NEXT:    ret
521  %vc = ashr <vscale x 4 x i32> %va, %vb
522  ret <vscale x 4 x i32> %vc
523}
524
525define <vscale x 4 x i32> @vsra_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
526; CHECK-LABEL: vsra_vx_nxv4i32:
527; CHECK:       # %bb.0:
528; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
529; CHECK-NEXT:    vsra.vx v8, v8, a0
530; CHECK-NEXT:    ret
531  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
532  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
533  %vc = ashr <vscale x 4 x i32> %va, %splat
534  ret <vscale x 4 x i32> %vc
535}
536
537define <vscale x 4 x i32> @vsra_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
538; CHECK-LABEL: vsra_vi_nxv4i32_0:
539; CHECK:       # %bb.0:
540; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
541; CHECK-NEXT:    vsra.vi v8, v8, 31
542; CHECK-NEXT:    ret
543  %head = insertelement <vscale x 4 x i32> poison, i32 31, i32 0
544  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
545  %vc = ashr <vscale x 4 x i32> %va, %splat
546  ret <vscale x 4 x i32> %vc
547}
548
549define <vscale x 8 x i32> @vsra_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
550; CHECK-LABEL: vsra_vv_nxv8i32:
551; CHECK:       # %bb.0:
552; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
553; CHECK-NEXT:    vsra.vv v8, v8, v12
554; CHECK-NEXT:    ret
555  %vc = ashr <vscale x 8 x i32> %va, %vb
556  ret <vscale x 8 x i32> %vc
557}
558
559define <vscale x 8 x i32> @vsra_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
560; CHECK-LABEL: vsra_vx_nxv8i32:
561; CHECK:       # %bb.0:
562; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
563; CHECK-NEXT:    vsra.vx v8, v8, a0
564; CHECK-NEXT:    ret
565  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
566  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
567  %vc = ashr <vscale x 8 x i32> %va, %splat
568  ret <vscale x 8 x i32> %vc
569}
570
571define <vscale x 8 x i32> @vsra_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
572; CHECK-LABEL: vsra_vi_nxv8i32_0:
573; CHECK:       # %bb.0:
574; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
575; CHECK-NEXT:    vsra.vi v8, v8, 31
576; CHECK-NEXT:    ret
577  %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
578  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
579  %vc = ashr <vscale x 8 x i32> %va, %splat
580  ret <vscale x 8 x i32> %vc
581}
582
583define <vscale x 16 x i32> @vsra_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
584; CHECK-LABEL: vsra_vv_nxv16i32:
585; CHECK:       # %bb.0:
586; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
587; CHECK-NEXT:    vsra.vv v8, v8, v16
588; CHECK-NEXT:    ret
589  %vc = ashr <vscale x 16 x i32> %va, %vb
590  ret <vscale x 16 x i32> %vc
591}
592
593define <vscale x 16 x i32> @vsra_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
594; CHECK-LABEL: vsra_vx_nxv16i32:
595; CHECK:       # %bb.0:
596; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
597; CHECK-NEXT:    vsra.vx v8, v8, a0
598; CHECK-NEXT:    ret
599  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
600  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
601  %vc = ashr <vscale x 16 x i32> %va, %splat
602  ret <vscale x 16 x i32> %vc
603}
604
605define <vscale x 16 x i32> @vsra_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
606; CHECK-LABEL: vsra_vi_nxv16i32_0:
607; CHECK:       # %bb.0:
608; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
609; CHECK-NEXT:    vsra.vi v8, v8, 31
610; CHECK-NEXT:    ret
611  %head = insertelement <vscale x 16 x i32> poison, i32 31, i32 0
612  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
613  %vc = ashr <vscale x 16 x i32> %va, %splat
614  ret <vscale x 16 x i32> %vc
615}
616
617define <vscale x 1 x i64> @vsra_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
618; CHECK-LABEL: vsra_vv_nxv1i64:
619; CHECK:       # %bb.0:
620; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
621; CHECK-NEXT:    vsra.vv v8, v8, v9
622; CHECK-NEXT:    ret
623  %vc = ashr <vscale x 1 x i64> %va, %vb
624  ret <vscale x 1 x i64> %vc
625}
626
627define <vscale x 1 x i64> @vsra_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
628; CHECK-LABEL: vsra_vx_nxv1i64:
629; CHECK:       # %bb.0:
630; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
631; CHECK-NEXT:    vsra.vx v8, v8, a0
632; CHECK-NEXT:    ret
633  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
634  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
635  %vc = ashr <vscale x 1 x i64> %va, %splat
636  ret <vscale x 1 x i64> %vc
637}
638
639define <vscale x 1 x i64> @vsra_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
640; CHECK-LABEL: vsra_vi_nxv1i64_0:
641; CHECK:       # %bb.0:
642; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
643; CHECK-NEXT:    vsra.vi v8, v8, 31
644; CHECK-NEXT:    ret
645  %head = insertelement <vscale x 1 x i64> poison, i64 31, i32 0
646  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
647  %vc = ashr <vscale x 1 x i64> %va, %splat
648  ret <vscale x 1 x i64> %vc
649}
650
651define <vscale x 1 x i64> @vsra_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
652; CHECK-LABEL: vsra_vi_nxv1i64_1:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    li a0, 32
655; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
656; CHECK-NEXT:    vsra.vx v8, v8, a0
657; CHECK-NEXT:    ret
658  %head = insertelement <vscale x 1 x i64> poison, i64 32, i32 0
659  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
660  %vc = ashr <vscale x 1 x i64> %va, %splat
661  ret <vscale x 1 x i64> %vc
662}
663
664define <vscale x 2 x i64> @vsra_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
665; CHECK-LABEL: vsra_vv_nxv2i64:
666; CHECK:       # %bb.0:
667; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
668; CHECK-NEXT:    vsra.vv v8, v8, v10
669; CHECK-NEXT:    ret
670  %vc = ashr <vscale x 2 x i64> %va, %vb
671  ret <vscale x 2 x i64> %vc
672}
673
674define <vscale x 2 x i64> @vsra_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
675; CHECK-LABEL: vsra_vx_nxv2i64:
676; CHECK:       # %bb.0:
677; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
678; CHECK-NEXT:    vsra.vx v8, v8, a0
679; CHECK-NEXT:    ret
680  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
681  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
682  %vc = ashr <vscale x 2 x i64> %va, %splat
683  ret <vscale x 2 x i64> %vc
684}
685
686define <vscale x 2 x i64> @vsra_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
687; CHECK-LABEL: vsra_vi_nxv2i64_0:
688; CHECK:       # %bb.0:
689; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
690; CHECK-NEXT:    vsra.vi v8, v8, 31
691; CHECK-NEXT:    ret
692  %head = insertelement <vscale x 2 x i64> poison, i64 31, i32 0
693  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
694  %vc = ashr <vscale x 2 x i64> %va, %splat
695  ret <vscale x 2 x i64> %vc
696}
697
698define <vscale x 2 x i64> @vsra_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
699; CHECK-LABEL: vsra_vi_nxv2i64_1:
700; CHECK:       # %bb.0:
701; CHECK-NEXT:    li a0, 32
702; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
703; CHECK-NEXT:    vsra.vx v8, v8, a0
704; CHECK-NEXT:    ret
705  %head = insertelement <vscale x 2 x i64> poison, i64 32, i32 0
706  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
707  %vc = ashr <vscale x 2 x i64> %va, %splat
708  ret <vscale x 2 x i64> %vc
709}
710
711define <vscale x 4 x i64> @vsra_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
712; CHECK-LABEL: vsra_vv_nxv4i64:
713; CHECK:       # %bb.0:
714; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
715; CHECK-NEXT:    vsra.vv v8, v8, v12
716; CHECK-NEXT:    ret
717  %vc = ashr <vscale x 4 x i64> %va, %vb
718  ret <vscale x 4 x i64> %vc
719}
720
721define <vscale x 4 x i64> @vsra_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
722; CHECK-LABEL: vsra_vx_nxv4i64:
723; CHECK:       # %bb.0:
724; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
725; CHECK-NEXT:    vsra.vx v8, v8, a0
726; CHECK-NEXT:    ret
727  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
728  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
729  %vc = ashr <vscale x 4 x i64> %va, %splat
730  ret <vscale x 4 x i64> %vc
731}
732
733define <vscale x 4 x i64> @vsra_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
734; CHECK-LABEL: vsra_vi_nxv4i64_0:
735; CHECK:       # %bb.0:
736; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
737; CHECK-NEXT:    vsra.vi v8, v8, 31
738; CHECK-NEXT:    ret
739  %head = insertelement <vscale x 4 x i64> poison, i64 31, i32 0
740  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
741  %vc = ashr <vscale x 4 x i64> %va, %splat
742  ret <vscale x 4 x i64> %vc
743}
744
745define <vscale x 4 x i64> @vsra_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
746; CHECK-LABEL: vsra_vi_nxv4i64_1:
747; CHECK:       # %bb.0:
748; CHECK-NEXT:    li a0, 32
749; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
750; CHECK-NEXT:    vsra.vx v8, v8, a0
751; CHECK-NEXT:    ret
752  %head = insertelement <vscale x 4 x i64> poison, i64 32, i32 0
753  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
754  %vc = ashr <vscale x 4 x i64> %va, %splat
755  ret <vscale x 4 x i64> %vc
756}
757
758define <vscale x 8 x i64> @vsra_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
759; CHECK-LABEL: vsra_vv_nxv8i64:
760; CHECK:       # %bb.0:
761; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
762; CHECK-NEXT:    vsra.vv v8, v8, v16
763; CHECK-NEXT:    ret
764  %vc = ashr <vscale x 8 x i64> %va, %vb
765  ret <vscale x 8 x i64> %vc
766}
767
768define <vscale x 8 x i64> @vsra_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
769; CHECK-LABEL: vsra_vx_nxv8i64:
770; CHECK:       # %bb.0:
771; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
772; CHECK-NEXT:    vsra.vx v8, v8, a0
773; CHECK-NEXT:    ret
774  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
775  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
776  %vc = ashr <vscale x 8 x i64> %va, %splat
777  ret <vscale x 8 x i64> %vc
778}
779
780define <vscale x 8 x i64> @vsra_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
781; CHECK-LABEL: vsra_vi_nxv8i64_0:
782; CHECK:       # %bb.0:
783; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
784; CHECK-NEXT:    vsra.vi v8, v8, 31
785; CHECK-NEXT:    ret
786  %head = insertelement <vscale x 8 x i64> poison, i64 31, i32 0
787  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
788  %vc = ashr <vscale x 8 x i64> %va, %splat
789  ret <vscale x 8 x i64> %vc
790}
791
792define <vscale x 8 x i64> @vsra_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
793; CHECK-LABEL: vsra_vi_nxv8i64_1:
794; CHECK:       # %bb.0:
795; CHECK-NEXT:    li a0, 32
796; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
797; CHECK-NEXT:    vsra.vx v8, v8, a0
798; CHECK-NEXT:    ret
799  %head = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
800  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
801  %vc = ashr <vscale x 8 x i64> %va, %splat
802  ret <vscale x 8 x i64> %vc
803}
804
805