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Searched refs:getVT (Results 1 – 25 of 44) sorted by relevance

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/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DScalableVectorMVTsTest.cpp98 MVT Mnxv8i64 = MVT::getVT(ScV8Int64Ty); in TEST()
101 ASSERT_EQ(MVT::getVT(ScV8Int64Ty->getElementType()), in TEST()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DDAGISelMatcherEmitter.cpp666 << getEnumName(cast<EmitIntegerMatcher>(N)->getVT()) << ", "; in EmitMatcher()
675 << getEnumName(cast<EmitStringIntegerMatcher>(N)->getVT()) << ", " << Val in EmitMatcher()
686 OS << "OPC_EmitRegister2, " << getEnumName(Matcher->getVT()) << ", "; in EmitMatcher()
690 OS << "OPC_EmitRegister, " << getEnumName(Matcher->getVT()) << ", "; in EmitMatcher()
793 OS << getEnumName(EN->getVT(i)) << ", "; in EmitMatcher()
H A DDAGISelMatcher.h825 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
849 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
874 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
1018 MVT::SimpleValueType getVT(unsigned i) const { in getVT() function
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp151 cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) { in selectSExti32()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DValueTypes.cpp541 MVT MVT::getVT(Type *Ty, bool HandleUnknown){ in getVT() function in MVT
564 getVT(VTy->getElementType(), /*HandleUnknown=*/ false), in getVT()
576 return MVT::getVT(Ty, HandleUnknown); in getEVT()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp728 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits(); in Select()
801 cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32) { in Select()
816 cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32; in Select()
1994 cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) { in selectSExti32()
H A DRISCVInstrInfo.td1140 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1144 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp562 MVT VT = MVT::getVT(Shuffles[0]->getType()); in deinterleave8bitStride3()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1106 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps()
3366 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3507 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3768 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3951 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
3954 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
6077 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
6089 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
6141 assert(!cast<VTSDNode>(N2)->getVT().isVector() && in getNode()
6143 assert(cast<VTSDNode>(N2)->getVT().bitsLE(VT.getScalarType()) && in getNode()
[all …]
H A DSelectionDAGDumper.cpp696 OS << ":" << N->getVT().getEVTString(); in print_details()
H A DSelectionDAGISel.cpp2575 if (cast<VTSDNode>(N)->getVT() == VT) in CheckValueType()
2579 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL); in CheckValueType()
H A DTargetLowering.cpp815 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyMultipleUseDemandedBits()
2161 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
2415 EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
4415 !isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(), in SimplifySetCC()
4417 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); in SimplifySetCC()
4520 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) in SimplifySetCC()
9537 EVT SatVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); in expandFP_TO_INT_SAT()
H A DLegalizeVectorOps.cpp985 EVT OrigTy = cast<VTSDNode>(Node->getOperand(1))->getVT(); in ExpandSEXTINREG()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1467 : cast<VTSDNode>(N.getOperand(1))->getVT(); in DetectUseSxtw()
1536 if (T->getVT().getSizeInBits() == NumBits) { in keepsLowBits()
1609 return VN->getVT().getSizeInBits() <= 16; in isPositiveHalfWord()
H A DHexagonISelLowering.cpp1061 EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerSETCC()
2078 Info.memVT = MVT::getVT(ElTy); in getTgtMemIntrinsic()
2103 Info.memVT = MVT::getVT(VecTy); in getTgtMemIntrinsic()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp222 unsigned Width = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in LowerSIGN_EXTEND_INREG()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DMachineValueType.h1451 static MVT getVT(Type *Ty, bool HandleUnknown = false);
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3847 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerVectorFP_TO_INT_SAT()
3919 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
12453 Info.memVT = MVT::getVT(ValTy); in getTgtMemIntrinsic()
12464 Info.memVT = MVT::getVT(ValTy); in getTgtMemIntrinsic()
12492 Info.memVT = MVT::getVT(I.getType()); in getTgtMemIntrinsic()
12503 Info.memVT = MVT::getVT(I.getOperand(0)->getType()); in getTgtMemIntrinsic()
12514 Info.memVT = MVT::getVT(Val->getType()); in getTgtMemIntrinsic()
14117 return TypeNode->getVT(); in calculatePreExtendType()
14925 MemVT = cast<VTSDNode>(Src->getOperand(3))->getVT(); in performSVEAndCombine()
17949 if ((TypeNode->getVT() == MVT::i8 && width == 8) in checkValueWidth()
[all …]
H A DAArch64ISelDAGToDAG.cpp636 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in getExtendTypeForNode()
1990 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits(); in isBitfieldExtractOpFromSExtInReg()
5137 return cast<VTSDNode>(Root->getOperand(3))->getVT(); in getMemVTFromNode()
5139 return cast<VTSDNode>(Root->getOperand(4))->getVT(); in getMemVTFromNode()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp400 LLT OldLLT(MVT::getVT(CurArgInfo.Ty)); in lowerReturn()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp917 MVT VT = MVT::getVT(Outs[I].Ty); in checkReturn()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1952 cast<VTSDNode>(Op.getOperand(1).getNode())->getVT().getSimpleVT(); in LowerSIGN_EXTEND_INREG()
2419 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1017 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType()); in getTgtMemIntrinsic()
1048 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1066 Info.memVT = MVT::getVT(CI.getOperand(0)->getType()); in getTgtMemIntrinsic()
1080 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1093 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1104 Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT? in getTgtMemIntrinsic()
1124 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
9930 VTSign->getVT() == MVT::i8) || in performSignExtendInRegCombine()
9932 VTSign->getVT() == MVT::i16)) && in performSignExtendInRegCombine()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td950 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
951 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp502 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); in performANDCombine()
910 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); in performSRACombine()

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