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Searched refs:addRegisterClass (Results 1 – 25 of 29) sorted by relevance

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/llvm-project-15.0.7/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp72 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass() function in __anon92a9f3a60111::RegisterBank
292 Bank.addRegisterClass(RC); in run()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp30 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
31 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
32 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
33 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
34 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
35 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
44 addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
45 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
46 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
54 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
[all …]
H A DHexagonISelLowering.cpp1466 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering()
1467 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering()
1470 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1471 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1472 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1473 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1474 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1475 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1476 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1478 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp60 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
61 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
62 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
63 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
65 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
66 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
67 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
68 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
69 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
70 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp40 addRegisterClass(MVT::i32, &CSKY::GPRRegClass); in CSKYTargetLowering()
44 addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass); in CSKYTargetLowering()
46 addRegisterClass(MVT::f32, &CSKY::FPR32RegClass); in CSKYTargetLowering()
49 addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass); in CSKYTargetLowering()
51 addRegisterClass(MVT::f64, &CSKY::FPR64RegClass); in CSKYTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp80 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
81 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
83 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
84 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
86 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
91 addRegisterClass(MVT::f64, V64RegClass); in SITargetLowering()
92 addRegisterClass(MVT::v2f32, V64RegClass); in SITargetLowering()
94 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass); in SITargetLowering()
97 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass); in SITargetLowering()
131 addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass); in SITargetLowering()
[all …]
H A DR600ISelLowering.cpp32 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
33 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp85 addRegisterClass(MVT::i32, &VE::I32RegClass); in initRegisterClasses()
86 addRegisterClass(MVT::i64, &VE::I64RegClass); in initRegisterClasses()
87 addRegisterClass(MVT::f32, &VE::F32RegClass); in initRegisterClasses()
88 addRegisterClass(MVT::f64, &VE::I64RegClass); in initRegisterClasses()
89 addRegisterClass(MVT::f128, &VE::F128RegClass); in initRegisterClasses()
93 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()
94 addRegisterClass(MVT::v256i1, &VE::VMRegClass); in initRegisterClasses()
95 addRegisterClass(MVT::v512i1, &VE::VM512RegClass); in initRegisterClasses()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp41 addRegisterClass(GRLenVT, &LoongArch::GPRRegClass); in LoongArchTargetLowering()
43 addRegisterClass(MVT::f32, &LoongArch::FPR32RegClass); in LoongArchTargetLowering()
45 addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass); in LoongArchTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
89 addRegisterClass(VecTy, &Mips::DSPRRegClass); in MipsSETargetLowering()
124 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass); in MipsSETargetLowering()
165 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsSETargetLowering()
170 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering()
172 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
312 addRegisterClass(Ty, RC); in addMSAIntType()
366 addRegisterClass(Ty, RC); in addMSAFloatType()
H A DMips16ISelLowering.cpp125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in Mips16TargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp61 addRegisterClass(MVT::i64, &BPF::GPRRegClass); in BPFTargetLowering()
63 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); in BPFTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp394 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass); in NVPTXTargetLowering()
395 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
396 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
397 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass); in NVPTXTargetLowering()
398 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass); in NVPTXTargetLowering()
399 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass); in NVPTXTargetLowering()
400 addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass); in NVPTXTargetLowering()
401 addRegisterClass(MVT::v2f16, &NVPTX::Float16x2RegsRegClass); in NVPTXTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp89 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); in SystemZTargetLowering()
91 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass); in SystemZTargetLowering()
92 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass); in SystemZTargetLowering()
95 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass); in SystemZTargetLowering()
96 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass); in SystemZTargetLowering()
98 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass); in SystemZTargetLowering()
99 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass); in SystemZTargetLowering()
102 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
104 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass); in SystemZTargetLowering()
107 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1517 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1519 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1520 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1521 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1524 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
1528 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); in SparcTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp295 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering()
296 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering()
305 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
306 addRegisterClass(MVT::bf16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
307 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
308 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
313 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
367 addRegisterClass(VT, &AArch64::ZPRRegClass); in AArch64TargetLowering()
371 addRegisterClass(VT, &AArch64::ZPRRegClass); in AArch64TargetLowering()
1716 addRegisterClass(VT, &AArch64::FPR64RegClass); in addDRTypeForNEON()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp166 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
169 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
172 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
174 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
175 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
294 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
723 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
920 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
921 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
922 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp49 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
50 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp100 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp58 addRegisterClass(MVT::i8, &M68k::DR8RegClass); in M68kTargetLowering()
59 addRegisterClass(MVT::i16, &M68k::XR16RegClass); in M68kTargetLowering()
60 addRegisterClass(MVT::i32, &M68k::XR32RegClass); in M68kTargetLowering()
/llvm-project-15.0.7/llvm/docs/
H A DWritingAnLLVMBackend.rst1349 ``addRegisterClass`` method to specify which types are supported and which
1358 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
1359 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1360 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp40 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); in AVRTargetLowering()
41 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp174 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
175 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
176 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
178 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
677 addRegisterClass(MVT::f32, &X86::FR32RegClass); in X86TargetLowering()
679 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering()
709 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering()
710 addRegisterClass(MVT::f32, &X86::RFP32RegClass); in X86TargetLowering()
767 addRegisterClass(MVT::f80, &X86::RFP80RegClass); in X86TargetLowering()
1583 addRegisterClass(MVT::v1i1, &X86::VK1RegClass); in X86TargetLowering()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp77 addRegisterClass(MVT::i32, &Lanai::GPRRegClass); in LanaiTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp217 addRegisterClass(VT, &ARM::DPRRegClass); in addDRTypeForNEON()
222 addRegisterClass(VT, &ARM::DPairRegClass); in addQRTypeForNEON()
250 addRegisterClass(VT, &ARM::MQPRRegClass); in addMVEVectorTypes()
325 addRegisterClass(VT, &ARM::MQPRRegClass); in addMVEVectorTypes()
393 addRegisterClass(VT, &ARM::MQPRRegClass); in addMVEVectorTypes()
439 addRegisterClass(VT, &ARM::VCCRRegClass); in addMVEVectorTypes()
766 addRegisterClass(MVT::i32, &ARM::tGPRRegClass); in ARMTargetLowering()
768 addRegisterClass(MVT::i32, &ARM::GPRRegClass); in ARMTargetLowering()
772 addRegisterClass(MVT::f32, &ARM::SPRRegClass); in ARMTargetLowering()
773 addRegisterClass(MVT::f64, &ARM::DPRRegClass); in ARMTargetLowering()
[all …]

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