80   addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);  in SITargetLowering()
81   addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);  in SITargetLowering()
83   addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
84   addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);  in SITargetLowering()
86   addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);  in SITargetLowering()
91   addRegisterClass(MVT::f64, V64RegClass);  in SITargetLowering()
92   addRegisterClass(MVT::v2f32, V64RegClass);  in SITargetLowering()
94   addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);  in SITargetLowering()
95   addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));  in SITargetLowering()
97   addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
98   addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
100   addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
101   addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));  in SITargetLowering()
103   addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);  in SITargetLowering()
104   addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));  in SITargetLowering()
106   addRegisterClass(MVT::v6i32, &AMDGPU::SGPR_192RegClass);  in SITargetLowering()
107   addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192));  in SITargetLowering()
109   addRegisterClass(MVT::v3i64, &AMDGPU::SGPR_192RegClass);  in SITargetLowering()
110   addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192));  in SITargetLowering()
112   addRegisterClass(MVT::v7i32, &AMDGPU::SGPR_224RegClass);  in SITargetLowering()
113   addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224));  in SITargetLowering()
115   addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);  in SITargetLowering()
116   addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));  in SITargetLowering()
118   addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);  in SITargetLowering()
119   addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));  in SITargetLowering()
121   addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);  in SITargetLowering()
122   addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));  in SITargetLowering()
124   addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);  in SITargetLowering()
125   addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));  in SITargetLowering()
127   addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);  in SITargetLowering()
128   addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));  in SITargetLowering()
131     addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
132     addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
135     addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
136     addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
137     addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);  in SITargetLowering()
138     addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);  in SITargetLowering()
139     addRegisterClass(MVT::v8i16, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
140     addRegisterClass(MVT::v8f16, &AMDGPU::SGPR_128RegClass);  in SITargetLowering()
141     addRegisterClass(MVT::v16i16, &AMDGPU::SGPR_256RegClass);  in SITargetLowering()
142     addRegisterClass(MVT::v16f16, &AMDGPU::SGPR_256RegClass);  in SITargetLowering()
145   addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);  in SITargetLowering()
146   addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));  in SITargetLowering()