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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvec_xxpermdi.ll70 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1>
79 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1>
88 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0>
140 define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) {
149 define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) {
157 define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
165 define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {
247 define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) {
256 define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) {
264 define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
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H A Dvec_sldwi.ll68 define <4 x i32> @check_le_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) {
76 define <4 x i32> @check_le_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) {
85 define <4 x i32> @check_le_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) {
139 define <4 x i32> @check_le_vec_sldwi_va_undef_0(<4 x i32> %VA) {
147 define <4 x i32> @check_le_vec_sldwi_va_undef_1(<4 x i32> %VA) {
156 define <4 x i32> @check_le_vec_sldwi_va_undef_2(<4 x i32> %VA) {
165 define <4 x i32> @check_le_vec_sldwi_va_undef_3(<4 x i32> %VA) {
245 define <4 x i32> @check_be_vec_sldwi_va_undef_0(<4 x i32> %VA) {
253 define <4 x i32> @check_be_vec_sldwi_va_undef_1(<4 x i32> %VA) {
262 define <4 x i32> @check_be_vec_sldwi_va_undef_2(<4 x i32> %VA) {
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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Darguments-varargs.ll65 ; Increment [[VA]]
99 ; Increment [[VA]] again.
180 ; Increment [[VA]]
214 ; Increment [[VA]] again.
331 ; Increment [[VA]] again.
417 ; Increment [[VA]]
451 ; Increment [[VA]] again.
532 ; Increment [[VA]]
566 ; Increment [[VA]] again.
768 ; Increment [[VA]]
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp113 CCValAssign VA) override { in assignValueToReg()
138 CCValAssign VA = VAs[0]; in assignCustomValue() local
142 if (VA.getValVT() != MVT::f64) in assignCustomValue()
149 assert(VA.getValNo() == NextVA.getValNo() && in assignCustomValue()
165 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
170 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
259 if (VA.getLocInfo() == CCValAssign::SExt || in assignValueToAddress()
260 VA.getLocInfo() == CCValAssign::ZExt) { in assignValueToAddress()
313 CCValAssign VA = VAs[0]; in assignCustomValue() local
317 if (VA.getValVT() != MVT::f64) in assignCustomValue()
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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmadak.ll12 ; GFX6: buffer_load_dword [[VA:v[0-9]+]]
14 ; GFX8: {{flat|global}}_load_dword [[VA:v[0-9]+]]
16 ; GFX9: {{flat|global}}_load_dword [[VA:v[0-9]+]]
18 ; GFX10: {{flat|global}}_load_dword [[VA:v[0-9]+]]
55 ; MAD-DAG: v_mac_f32_e32 [[VK]], [[VA]], [[VC]]
105 ; GFX6: buffer_load_dword [[VA:v[0-9]+]]
107 ; GFX8: {{flat|global}}_load_dword [[VA:v[0-9]+]]
109 ; GFX9: {{flat|global}}_load_dword [[VA:v[0-9]+]]
111 ; GFX10: {{flat|global}}_load_dword [[VA:v[0-9]+]]
190 ; GFX6: buffer_load_dword [[VA:v[0-9]+]]
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/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp192 EVT LocVT = VA.getLocVT(); in convertValVTToLocVT()
282 (VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::i64) && in unpack64()
288 if (VA.isMemLoc()) { in unpack64()
346 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerFormalArguments()
350 else if (VA.isRegLoc()) in LowerFormalArguments()
449 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerReturn()
476 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
567 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerCall()
602 if (VA.isRegLoc()) { in LowerCall()
718 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
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/llvm-project-15.0.7/llvm/unittests/XRay/
H A DGraphTest.cpp20 unsigned VA; member
66 std::vector<unsigned> VA({0u, 3u, 5u, 7u, 11u, 13u, 17u}); in graphVertexTester() local
74 EXPECT_EQ(VA[u], EVV->VA); in graphVertexTester()
83 EXPECT_EQ(VA[VVT.first], VVT.second.VA); in graphVertexTester()
92 std::vector<unsigned> VA({0u, 3u, 5u, 7u, 11u, 13u, 17u}); in graphEdgeTester() local
100 EXPECT_EQ(VA[u.first] * VA[u.second] * ((u.first > u.second) ? 2 : 1), in graphEdgeTester()
110 EXPECT_EQ(VA[EV.first.first] * VA[EV.first.second] * in graphEdgeTester()
203 EXPECT_EQ(1u, MG[0u].VA); in TEST()
206 EXPECT_EQ(1u, MG[0u].VA); in TEST()
209 EXPECT_EQ(1u, T->VA); in TEST()
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/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp305 switch (VA.getLocInfo()) { in LowerCall()
323 if (VA.isRegLoc()) { in LowerCall()
416 if (VA.isRegLoc()) { in lowerCallResult()
419 DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue); in lowerCallResult()
521 if (VA.isRegLoc()) { in LowerCallArguments()
523 EVT RegVT = VA.getLocVT(); in LowerCallArguments()
538 assert(VA.isMemLoc()); in LowerCallArguments()
673 if (VA.isRegLoc()) in LowerReturn()
675 assert(VA.isMemLoc()); in LowerReturn()
701 if (!VA.isRegLoc()) in LowerReturn()
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/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp307 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
384 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerReturn_64()
402 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
555 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { in LowerFormalArguments_32()
650 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerFormalArguments_64()
1166 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1177 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1252 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1259 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1287 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerCall_64()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepIICHVX.td145 InstrItinData <tc_0ec46cf9, /*SLOT0123,VA*/
199 InstrItinData <tc_257f6f7c, /*SLOT0123,VA*/
244 InstrItinData <tc_3aacf4a8, /*SLOT0123,VA*/
309 InstrItinData <tc_540c3da3, /*SLOT0,VA*/
325 InstrItinData <tc_56c4f9fe, /*SLOT0123,VA*/
873 InstrItinData <tc_540c3da3, /*SLOT0,VA*/
1437 InstrItinData <tc_540c3da3, /*SLOT0,VA*/
2001 InstrItinData <tc_540c3da3, /*SLOT0,VA*/
2565 InstrItinData <tc_540c3da3, /*SLOT0,VA*/
3129 InstrItinData <tc_540c3da3, /*SLOT0,VA*/
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/llvm-project-15.0.7/lld/test/ELF/
H A Dgot32-i386-pie-rw.s33 ## ^--- VA of GOT entry (0x31f0)
35 ## ^--- VA of GOT entry in Elf_Rela addend
38 ## ^--- VA of foo (0x1180)
40 ## ^--- VA of foo in Elf_Rela addend
45 ## ^--- VA of GOT entry (0x31f0)
47 ## ^--- VA of GOT entry in in Elf_Rela addend
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp72 const MVT ValVT = VA.getValVT(); in getStackValueStoreTypeHack()
157 return getStackValueStoreTypeHack(VA); in getStackValueStoreType()
170 LLT ValTy(VA.getValVT()); in assignValueToAddress()
171 LLT LocTy(VA.getLocVT()); in assignValueToAddress()
174 if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16) in assignValueToAddress()
187 switch (VA.getLocInfo()) { in assignValueToAddress()
311 MVT LocVT = VA.getLocVT(); in assignValueToAddress()
312 MVT ValVT = VA.getValVT(); in assignValueToAddress()
314 if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16) { in assignValueToAddress()
316 MemTy = LLT(VA.getValVT()); in assignValueToAddress()
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/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp653 CCValAssign &VA = ArgLocs[j]; in handleAssignments() local
656 if (VA.needsCustom()) { in handleAssignments()
783 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
786 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
1066 const MVT ValVT = VA.getValVT(); in getStackValueStoreType()
1091 CCValAssign &VA) const { in copyArgumentMemory()
1113 LLT LocTy{VA.getLocVT()}; in extendRegister()
1114 LLT ValTy{VA.getValVT()}; in extendRegister()
1133 switch (VA.getLocInfo()) { in extendRegister()
1163 switch (VA.getLocInfo()) { in buildExtensionHint()
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/llvm-project-15.0.7/llvm/test/Demangle/
H A Dms-return-qualifiers.test97 ?d3@@YA?AV?$B@VA@@@@XZ
100 ?d4@@YAPAV?$B@VA@@@@XZ
103 ?d5@@YAPBV?$B@VA@@@@XZ
106 ?d6@@YAPCV?$B@VA@@@@XZ
109 ?d7@@YAPDV?$B@VA@@@@XZ
112 ?d8@@YAAAV?$B@VA@@@@XZ
115 ?d9@@YAABV?$B@VA@@@@XZ
118 ?d10@@YAACV?$B@VA@@@@XZ
121 ?d11@@YAADV?$B@VA@@@@XZ
/llvm-project-15.0.7/llvm/test/tools/llvm-pdbutil/
H A Dload-address.test6 ; RUN: %p/Inputs/LoadAddressTest.pdb | FileCheck --check-prefix=VA %s
11 ; VA: ---EXTERNALS---
12 ; VA: [0x40001010] _main
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp320 for (auto &VA : ArgLocs) { in LowerFormalArguments() local
321 if (VA.isRegLoc()) { in LowerFormalArguments()
323 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
335 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
340 if (VA.getLocInfo() == CCValAssign::SExt) in LowerFormalArguments()
347 if (VA.getLocInfo() != CCValAssign::Full) in LowerFormalArguments()
421 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
425 switch (VA.getLocInfo()) { in LowerCall()
442 if (VA.isRegLoc()) in LowerCall()
528 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
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/llvm-project-15.0.7/clang/test/Parser/
H A Dcxx-using-declaration.cpp4 int VA; variable
9 using A::VA;
15 VA = 1; in main()
/llvm-project-15.0.7/clang/test/CXX/special/class.dtor/
H A Dp3-0x.cpp140 struct VA { struct
142 virtual ~VA() {} in ~VA() argument
145 struct VB : VA
149 struct TVB : VA
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp393 ValVT = VA.getLocVT(); in LowerMemArgument()
395 ValVT = VA.getValVT(); in LowerMemArgument()
444 return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val) in LowerMemArgument()
630 if (VA.isRegLoc()) { in LowerCall()
633 assert(VA.isMemLoc()); in LowerCall()
675 if (VA.isRegLoc()) in LowerCall()
677 assert(VA.isMemLoc()); in LowerCall()
857 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1) in LowerCallResult()
898 if (VA.isRegLoc()) { in LowerFormalArguments()
1057 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h259 const CCValAssign &VA,
266 CCValAssign VA) = 0;
273 CCValAssign &VA) = 0;
281 CCValAssign &VA) { in assignValueToAddress()
282 assignValueToAddress(Arg.Regs[ValRegIndex], Addr, MemTy, MPO, VA); in assignValueToAddress()
305 uint64_t MemSize, CCValAssign &VA) const;
309 Register extendRegister(Register ValReg, CCValAssign &VA,
321 Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy);
325 CCValAssign VA) override;
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp39 CCValAssign VA) override { in assignValueToReg()
41 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
46 MachinePointerInfo &MPO, CCValAssign &VA) override { in assignValueToAddress()
48 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
129 CCValAssign VA) { in assignValueToReg() argument
132 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
139 CCValAssign &VA) { in assignValueToAddress() argument
164 CCValAssign VA) { in assignValueToReg() argument
H A DM68kCallLowering.h56 CCValAssign VA) override;
59 MachinePointerInfo &MPO, CCValAssign &VA) override;
78 CCValAssign VA) override;
/llvm-project-15.0.7/llvm/lib/DebugInfo/PDB/Native/
H A DNativeSession.cpp220 bool NativeSession::addressForVA(uint64_t VA, uint32_t &Section, in addressForVA() argument
222 uint32_t RVA = VA - getLoadAddress(); in addressForVA()
293 uint64_t VA = getVAFromSectOffset(Section, Offset); in findLineNumbersBySectOffset() local
294 return Cache.findLineNumbersByVA(VA, Length); in findLineNumbersBySectOffset()
402 bool NativeSession::moduleIndexForVA(uint64_t VA, uint16_t &ModuleIndex) const { in moduleIndexForVA() argument
404 auto Iter = AddrToModuleIndex.find(VA); in moduleIndexForVA()
437 uint64_t VA = Session.getVAFromSectOffset(C.ISect, C.Off); in parseSectionContribs() local
438 uint64_t End = VA + C.Size; in parseSectionContribs()
442 if (!AddrMap.overlaps(VA, End)) in parseSectionContribs()
443 AddrMap.insert(VA, End, C.Imod); in parseSectionContribs()
/llvm-project-15.0.7/llvm/test/DebugInfo/PDB/
H A Dpdbdump-raw-stream.test15 … E207E554 01000000 0B355641 86A0A249 896F9988 FAE52FF0 22000000 |..1....T.....5VA...I.o..../."...|
29 … E207E554 01000000 0B355641 86A0A249 896F9988 FAE52FF0 22000000 |..1....T.....5VA...I.o..../."...|
40 …00B35 564186A0 A249896F 9988FAE5 2FF02200 00002F4C 696E6B49 6E666F00 |...5VA...I.o..../.".../Link…
50 …3000: 942E3101 E207E554 01000000 0B355641 86A0A249 |..1....T.....5VA...I|
57 …08: 01000000 0B355641 86A0A249 896F9988 FAE52FF0 |.....5VA...I.o..../.|
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp382 switch (VA.getLocInfo()) { in LowerReturn()
418 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
454 if (VA.isRegLoc()) { in LowerFormalArguments()
460 MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); in LowerFormalArguments()
493 if (VA.isExtInLoc()) in LowerFormalArguments()
501 assert(VA.isMemLoc()); in LowerFormalArguments()
680 switch (VA.getLocInfo()) { in LowerCall()
712 if (VA.isRegLoc()) { in LowerCall()
716 VA = ArgLocs2[i]; in LowerCall()
719 assert(VA.isMemLoc()); in LowerCall()
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