Lines Matching refs:VA
279 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
280 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
284 if (VA.needsCustom()) { in LowerReturn_32()
285 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
296 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
298 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
299 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
300 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
303 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
307 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
362 CCValAssign &VA = RVLocs[i]; in LowerReturn_64() local
363 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
367 switch (VA.getLocInfo()) { in LowerReturn_64()
370 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
373 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
376 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
384 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerReturn_64()
390 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
398 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
402 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
447 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_32() local
461 if (VA.isRegLoc()) { in LowerFormalArguments_32()
462 if (VA.needsCustom()) { in LowerFormalArguments_32()
463 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
466 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
489 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
494 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
496 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
498 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
500 DAG.getValueType(VA.getLocVT())); in LowerFormalArguments_32()
501 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
507 assert(VA.isMemLoc()); in LowerFormalArguments_32()
509 unsigned Offset = VA.getLocMemOffset()+StackOffset; in LowerFormalArguments_32()
512 if (VA.needsCustom()) { in LowerFormalArguments_32()
513 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32); in LowerFormalArguments_32()
521 DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo()); in LowerFormalArguments_32()
545 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue); in LowerFormalArguments_32()
555 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { in LowerFormalArguments_32()
556 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo()); in LowerFormalArguments_32()
557 } else if (VA.getValVT() == MVT::f128) { in LowerFormalArguments_32()
639 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_64() local
640 if (VA.isRegLoc()) { in LowerFormalArguments_64()
645 Register VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
646 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
647 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); in LowerFormalArguments_64()
650 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerFormalArguments_64()
651 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
656 switch (VA.getLocInfo()) { in LowerFormalArguments_64()
658 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
659 DAG.getValueType(VA.getValVT())); in LowerFormalArguments_64()
662 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
663 DAG.getValueType(VA.getValVT())); in LowerFormalArguments_64()
670 if (VA.isExtInLoc()) in LowerFormalArguments_64()
671 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerFormalArguments_64()
678 assert(VA.isMemLoc()); in LowerFormalArguments_64()
681 unsigned Offset = VA.getLocMemOffset() + ArgArea; in LowerFormalArguments_64()
682 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments_64()
686 if (VA.isExtInLoc()) in LowerFormalArguments_64()
690 DAG.getLoad(VA.getValVT(), DL, Chain, in LowerFormalArguments_64()
866 CCValAssign &VA = ArgLocs[i]; in LowerCall_32() local
880 switch (VA.getLocInfo()) { in LowerCall_32()
884 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
887 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
890 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
893 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
898 assert(VA.needsCustom()); in LowerCall_32()
917 if (VA.needsCustom()) { in LowerCall_32()
918 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerCall_32()
920 if (VA.isMemLoc()) { in LowerCall_32()
921 unsigned Offset = VA.getLocMemOffset() + StackOffset; in LowerCall_32()
933 if (VA.getLocVT() == MVT::f64) { in LowerCall_32()
949 if (VA.isRegLoc()) { in LowerCall_32()
950 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0)); in LowerCall_32()
965 unsigned Offset = VA.getLocMemOffset() + StackOffset; in LowerCall_32()
983 if (VA.isRegLoc()) { in LowerCall_32()
984 if (VA.getLocVT() != MVT::f32) { in LowerCall_32()
985 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
989 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
993 assert(VA.isMemLoc()); in LowerCall_32()
997 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset, in LowerCall_32()
1142 const CCValAssign &VA = ArgLocs[i]; in fixupVariableFloatArgs() local
1143 MVT ValTy = VA.getLocVT(); in fixupVariableFloatArgs()
1146 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1149 if (Outs[VA.getValNo()].IsFixed) in fixupVariableFloatArgs()
1158 unsigned Offset = argSize * (VA.getLocReg() - firstReg); in fixupVariableFloatArgs()
1166 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1172 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1177 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1178 Offset, VA.getLocVT(), VA.getLocInfo()); in fixupVariableFloatArgs()
1231 const CCValAssign &VA = ArgLocs[i]; in LowerCall_64() local
1235 switch (VA.getLocInfo()) { in LowerCall_64()
1241 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1244 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1247 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1252 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1253 || VA.getLocVT() != MVT::i128) in LowerCall_64()
1254 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1258 if (VA.isRegLoc()) { in LowerCall_64()
1259 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1260 && VA.getLocVT() == MVT::i128) { in LowerCall_64()
1262 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); in LowerCall_64()
1278 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), in LowerCall_64()
1280 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1), in LowerCall_64()
1287 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerCall_64()
1294 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerCall_64()
1302 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); in LowerCall_64()
1306 assert(VA.isMemLoc()); in LowerCall_64()
1312 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + in LowerCall_64()
1396 CCValAssign &VA = RVLocs[i]; in LowerCall_64() local
1397 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCall_64()
1398 unsigned Reg = toCallerWindow(VA.getLocReg()); in LowerCall_64()
1416 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerCall_64()
1417 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, in LowerCall_64()
1422 switch (VA.getLocInfo()) { in LowerCall_64()
1424 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
1425 DAG.getValueType(VA.getValVT())); in LowerCall_64()
1428 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
1429 DAG.getValueType(VA.getValVT())); in LowerCall_64()
1436 if (VA.isExtInLoc()) in LowerCall_64()
1437 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); in LowerCall_64()