320   for (auto &VA : ArgLocs) {  in LowerFormalArguments()  local
321     if (VA.isRegLoc()) {  in LowerFormalArguments()
323       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()
335         RegInfo.addLiveIn(VA.getLocReg(), VReg);  in LowerFormalArguments()
340         if (VA.getLocInfo() == CCValAssign::SExt)  in LowerFormalArguments()
342                                  DAG.getValueType(VA.getValVT()));  in LowerFormalArguments()
343         else if (VA.getLocInfo() == CCValAssign::ZExt)  in LowerFormalArguments()
345                                  DAG.getValueType(VA.getValVT()));  in LowerFormalArguments()
347         if (VA.getLocInfo() != CCValAssign::Full)  in LowerFormalArguments()
348           ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);  in LowerFormalArguments()
356       InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT()));  in LowerFormalArguments()
421     CCValAssign &VA = ArgLocs[i];  in LowerCall()  local
425     switch (VA.getLocInfo()) {  in LowerCall()
431       Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);  in LowerCall()
434       Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);  in LowerCall()
437       Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);  in LowerCall()
442     if (VA.isRegLoc())  in LowerCall()
443       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));  in LowerCall()
528     CCValAssign &VA = RVLocs[i];  in LowerReturn()  local
529     assert(VA.isRegLoc() && "Can only return in registers!");  in LowerReturn()
531     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);  in LowerReturn()
536     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));  in LowerReturn()