376     CCValAssign &VA = RVLocs[i];  in LowerReturn()  local
377     assert(VA.isRegLoc() && "Can only return in registers!");  in LowerReturn()
378     assert(!VA.needsCustom() && "Unexpected custom lowering");  in LowerReturn()
382     switch (VA.getLocInfo()) {  in LowerReturn()
386       OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);  in LowerReturn()
389       OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);  in LowerReturn()
392       OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);  in LowerReturn()
400       assert(VA.getLocVT() == MVT::i64);  in LowerReturn()
401       assert(VA.getValVT() == MVT::f32);  in LowerReturn()
414     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);  in LowerReturn()
418     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));  in LowerReturn()
452     CCValAssign &VA = ArgLocs[i];  in LowerFormalArguments()  local
453     assert(!VA.needsCustom() && "Unexpected custom lowering");  in LowerFormalArguments()
454     if (VA.isRegLoc()) {  in LowerFormalArguments()
460           MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));  in LowerFormalArguments()
461       SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());  in LowerFormalArguments()
465       switch (VA.getLocInfo()) {  in LowerFormalArguments()
467         Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,  in LowerFormalArguments()
468                           DAG.getValueType(VA.getValVT()));  in LowerFormalArguments()
471         Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,  in LowerFormalArguments()
472                           DAG.getValueType(VA.getValVT()));  in LowerFormalArguments()
480         assert(VA.getLocVT() == MVT::i64);  in LowerFormalArguments()
481         assert(VA.getValVT() == MVT::f32);  in LowerFormalArguments()
493       if (VA.isExtInLoc())  in LowerFormalArguments()
494         Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);  in LowerFormalArguments()
501     assert(VA.isMemLoc());  in LowerFormalArguments()
504     unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;  in LowerFormalArguments()
505     unsigned ValSize = VA.getValVT().getSizeInBits() / 8;  in LowerFormalArguments()
517     if (VA.getValVT() == MVT::f32)  in LowerFormalArguments()
522         DAG.getLoad(VA.getValVT(), DL, Chain,  in LowerFormalArguments()
676     CCValAssign &VA = ArgLocs[i];  in LowerCall()  local
680     switch (VA.getLocInfo()) {  in LowerCall()
686       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);  in LowerCall()
689       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);  in LowerCall()
692       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);  in LowerCall()
700       assert(VA.getLocVT() == MVT::i64);  in LowerCall()
701       assert(VA.getValVT() == MVT::f32);  in LowerCall()
712     if (VA.isRegLoc()) {  in LowerCall()
713       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));  in LowerCall()
716       VA = ArgLocs2[i];  in LowerCall()
719     assert(VA.isMemLoc());  in LowerCall()
725         DAG.getIntPtrConstant(VA.getLocMemOffset() + ArgsBaseOffset, DL);  in LowerCall()
792     CCValAssign &VA = RVLocs[i];  in LowerCall()  local
793     assert(!VA.needsCustom() && "Unexpected custom lowering");  in LowerCall()
794     Register Reg = VA.getLocReg();  in LowerCall()
813     switch (VA.getLocInfo()) {  in LowerCall()
815       RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,  in LowerCall()
816                        DAG.getValueType(VA.getValVT()));  in LowerCall()
819       RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,  in LowerCall()
820                        DAG.getValueType(VA.getValVT()));  in LowerCall()
828       assert(VA.getLocVT() == MVT::i64);  in LowerCall()
829       assert(VA.getValVT() == MVT::f32);  in LowerCall()
841     if (VA.isExtInLoc())  in LowerCall()
842       RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);  in LowerCall()