191                                    const CCValAssign &VA, const SDLoc &DL) {  in convertValVTToLocVT()  argument
192   EVT LocVT = VA.getLocVT();  in convertValVTToLocVT()
194   switch (VA.getLocInfo()) {  in convertValVTToLocVT()
207                                    const CCValAssign &VA, const SDLoc &DL) {  in convertLocVTToValVT()  argument
208   switch (VA.getLocInfo()) {  in convertLocVTToValVT()
214     Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);  in convertLocVTToValVT()
222                                 const CCValAssign &VA, const SDLoc &DL) {  in unpackFromRegLoc()  argument
225   EVT LocVT = VA.getLocVT();  in unpackFromRegLoc()
246   RegInfo.addLiveIn(VA.getLocReg(), VReg);  in unpackFromRegLoc()
249   return convertLocVTToValVT(DAG, Val, VA, DL);  in unpackFromRegLoc()
253                                 const CCValAssign &VA, const SDLoc &DL) {  in unpackFromMemLoc()  argument
256   EVT LocVT = VA.getLocVT();  in unpackFromMemLoc()
257   EVT ValVT = VA.getValVT();  in unpackFromMemLoc()
260                                  VA.getLocMemOffset(), /*Immutable=*/true);  in unpackFromMemLoc()
265   switch (VA.getLocInfo()) {  in unpackFromMemLoc()
279 static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA,  in unpack64()  argument
281   assert(VA.getLocVT() == MVT::i32 &&  in unpack64()
282          (VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::i64) &&  in unpack64()
288   if (VA.isMemLoc()) {  in unpack64()
290     int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true);  in unpack64()
292     return DAG.getLoad(VA.getValVT(), DL, Chain, FIN,  in unpack64()
296   assert(VA.isRegLoc() && "Expected register VA assignment");  in unpack64()
299   RegInfo.addLiveIn(VA.getLocReg(), LoVReg);  in unpack64()
302   if (VA.getLocReg() == CSKY::R3) {  in unpack64()
311     RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg);  in unpack64()
314   return DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(), Lo, Hi);  in unpack64()
343     CCValAssign &VA = ArgLocs[i];  in LowerFormalArguments()  local
346     bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;  in LowerFormalArguments()
349       ArgValue = unpack64(DAG, Chain, VA, DL);  in LowerFormalArguments()
350     else if (VA.isRegLoc())  in LowerFormalArguments()
351       ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL);  in LowerFormalArguments()
353       ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);  in LowerFormalArguments()
446     CCValAssign &VA = CSKYLocs[i];  in LowerReturn()  local
447     assert(VA.isRegLoc() && "Can only return in registers!");  in LowerReturn()
449     bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;  in LowerReturn()
453       assert(VA.isRegLoc() && "Expected return via registers");  in LowerReturn()
459       Register RegLo = VA.getLocReg();  in LowerReturn()
471       Val = convertValVTToLocVT(DAG, Val, VA, DL);  in LowerReturn()
472       Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);  in LowerReturn()
476       RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));  in LowerReturn()
563     CCValAssign &VA = ArgLocs[i];  in LowerCall()  local
567     bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;  in LowerCall()
569     if (IsF64OnCSKY && VA.isRegLoc()) {  in LowerCall()
576       Register RegLo = VA.getLocReg();  in LowerCall()
596     ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL);  in LowerCall()
602     if (VA.isRegLoc()) {  in LowerCall()
604       RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));  in LowerCall()
606       assert(VA.isMemLoc() && "Argument not register or memory");  in LowerCall()
615                       DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));  in LowerCall()
715   for (auto &VA : CSKYLocs) {  in LowerCall()  local
718         DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);  in LowerCall()
723     bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;  in LowerCall()
726       assert(VA.getLocReg() == GPRArgRegs[0] && "Unexpected reg assignment");  in LowerCall()
731       RetValue = DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(),  in LowerCall()
735     RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL);  in LowerCall()