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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMPredicates.td9 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
11 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
12 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
14 def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
15 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
20 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
53 def HasFPRegsV8_1M : Predicate<"Subtarget->hasFPRegs() && Subtarget->hasV8_1MMainlineOps()">,
188 …def UseMovtInPic : Predicate<"Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt(…
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H A DARMMachineFunctionInfo.cpp17 const auto &Subtarget = MF.getSubtarget<ARMSubtarget>(); in GetBranchTargetEnforcement() local
18 if (!Subtarget.isMClass() || !Subtarget.hasV7Ops()) in GetBranchTargetEnforcement()
71 const auto &Subtarget = MF.getSubtarget<ARMSubtarget>(); in ARMFunctionInfo() local
72 if (Subtarget.isMClass() && Subtarget.hasV7Ops()) in ARMFunctionInfo()
H A DARMSelectionDAGInfo.cpp41 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall() local
43 const ARMTargetLowering *TLI = Subtarget.getTargetLowering(); in EmitSpecializedLibcall()
142 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop() argument
164 Subtarget.getMaxMemcpyTPInlineSizeThreshold()) in shouldGenerateInlineTPLoop()
173 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy() local
177 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
192 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
203 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6; in EmitTargetCodeForMemcpy()
221 if (NumMEMCPYs > 1 && Subtarget.hasMinSize()) { in EmitTargetCodeForMemcpy()
302 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemset() local
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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp97 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
105 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
108 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
111 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
117 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
130 if (Subtarget.isABI_N64()) in getCallPreservedMask()
133 if (Subtarget.isABI_N32()) in getCallPreservedMask()
136 if (Subtarget.isFP64bit()) in getCallPreservedMask()
139 if (Subtarget.isFPXX()) in getCallPreservedMask()
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H A DMipsISelLowering.cpp464 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) in MipsTargetLowering()
1051 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && in performSUBCombine()
1066 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && in performADDCombine()
2029 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); in lowerBRCOND()
2644 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { in lowerShiftRightParts()
4591 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && in emitPseudoSELECT()
4668 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && in emitPseudoD_SELECT()
4779 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitLDR_W()
4825 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitLDR_D()
4909 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitSTR_W()
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H A DMipsAsmPrinter.cpp82 if (Subtarget->inMips16Mode()) in runOnMachineFunction()
92 if (Subtarget->isTargetNaCl()) in runOnMachineFunction()
117 if (Subtarget->hasMips64r6()) { in emitPseudoIndirectBranch()
405 if (Subtarget->isTargetNaCl()) in emitFunctionEntryLabel()
411 TS.updateABIInfo(*Subtarget); in emitFunctionEntryLabel()
415 if (Subtarget->inMips16Mode()) in emitFunctionEntryLabel()
438 if (!Subtarget->inMips16Mode()) { in emitFunctionBodyStart()
453 if (!Subtarget->inMips16Mode()) { in emitFunctionBodyEnd()
642 if (Subtarget->isLittle()) in PrintAsmMemoryOperand()
646 if (!Subtarget->isLittle()) in PrintAsmMemoryOperand()
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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dverify-gfx90a-aligned-vgprs.mir64 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
65 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
66 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
72 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
73 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
74 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
75 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
82 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
83 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
84 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
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H A Dverify-ds-gws-align.mir3 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS ins…
5 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS ins…
7 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS ins…
9 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS ins…
11 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS ins…
13 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS ins…
15 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for DS_GWS ins…
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCLowerMASSVEntries.cpp52 static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
57 const PPCSubtarget *Subtarget);
75 if (!Subtarget) in getCPUSuffix()
78 if (Subtarget->isAIXABI() && Subtarget->hasP10Vector()) in getCPUSuffix()
80 if (Subtarget->hasP9Vector()) in getCPUSuffix()
82 if (Subtarget->hasP8Vector()) in getCPUSuffix()
84 if (Subtarget->isAIXABI()) in getCPUSuffix()
97 StringRef Suffix = getCPUSuffix(Subtarget); in createMASSVFuncName()
144 std::string MASSVEntryName = createMASSVFuncName(Func, Subtarget); in lowerMASSVCall()
161 const PPCSubtarget *Subtarget; in runOnModule() local
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H A DPPCRegisterInfo.cpp190 if (Subtarget.hasVSX()) { in getCalleeSavedRegs()
217 if (Subtarget.isAIXABI()) in getCalleeSavedRegs()
250 if (Subtarget.isAIXABI()) { in getCalleeSavedRegs()
258 if (Subtarget.hasAltivec()) in getCalleeSavedRegs()
260 else if (Subtarget.hasSPE()) in getCalleeSavedRegs()
270 if (Subtarget.hasVSX()) { in getCallPreservedMask()
285 if (Subtarget.isAIXABI()) { in getCallPreservedMask()
378 if (Subtarget.isAIXABI()) in getReservedRegs()
405 if (Subtarget.isAIXABI() && Subtarget.hasAltivec() && in getReservedRegs()
525 if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI()) in isCallerPreservedPhysReg()
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H A DPPCFrameLowering.cpp85 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
231 if (Subtarget.is64BitELFABI()) { in getCalleeSavedSpillSlots()
236 if (Subtarget.is32BitELFABI()) { in getCalleeSavedSpillSlots()
243 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
541 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); in twoUniqueScratchRegsRequired()
570 if (!Subtarget.isELFv2ABI() || !Subtarget.isPPC64()) in stackUpdateCanBeMoved()
620 bool isPPC64 = Subtarget.isPPC64(); in emitPrologue()
1222 bool isPPC64 = Subtarget.isPPC64(); in inlineStackProbe()
1253 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); in inlineStackProbe()
1555 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); in emitEpilogue()
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H A DPPCISelLowering.cpp458 if (Subtarget.hasP9Vector() && Subtarget.isPPC64()) in PPCTargetLowering()
683 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
3176 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3183 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3200 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3792 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
8241 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
8532 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8680 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
9305 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td26 // Subtarget Features (device properties)
708 // Subtarget Features (options and debugging)
1466 Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1470 Predicate<"Subtarget->hasGFX90AInsts()">,
1474 Predicate<"!Subtarget->hasGFX90AInsts()">,
1484 Predicate<"Subtarget->hasGFX90AInsts() && !Subtarget->hasGFX940Insts()">,
1488 Predicate<"Subtarget->hasMAIInsts() && !Subtarget->hasGFX940Insts()">,
1492 Predicate<"Subtarget->hasGFX940Insts()">,
1496 Predicate<"Subtarget->hasGFX940Insts() ||"
1606 Predicate<"Subtarget->hasSDWA()">,
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCV.td30 : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
81 : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZfhmin()">,
118 : Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
204 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
224 : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkx()">,
230 : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
236 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
242 …: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()"…
253 : Predicate<"Subtarget->hasStdExtZbkc()">,
258 : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
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H A DRISCVISelLowering.cpp52 if (Subtarget.isRV32E()) in RISCVTargetLowering()
218 if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul()) { in RISCVTargetLowering()
245 if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp() || in RISCVTargetLowering()
357 if (Subtarget.hasStdExtF() && Subtarget.is64Bit()) in RISCVTargetLowering()
957 if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZbb()) in RISCVTargetLowering()
1149 return (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp() || in hasAndNotCompare()
7009 Subtarget.is64Bit() && Subtarget.hasStdExtM() && in ReplaceNodeResults()
8111 if (Subtarget.is64Bit() && Subtarget.hasStdExtZbs() && in performANDCombine()
8246 if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit() && in performSIGN_EXTEND_INREGCombine()
9484 if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) { in targetShrinkDemandedConstant()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp52 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
123 bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in EmitTargetCodeForMemset()
158 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepmovs()
180 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitRepmovsB()
185 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, in getOptimalRepmovsType() argument
197 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in getOptimalRepmovsType()
217 if (Subtarget.hasERMSB()) in emitConstantSizeRepmov()
220 assert(!Subtarget.hasERMSB() && "No efficient RepMovs"); in emitConstantSizeRepmov()
231 emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitConstantSizeRepmov()
276 const X86Subtarget &Subtarget = in EmitTargetCodeForMemcpy() local
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H A DX86ISelLowering.cpp136 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
362 if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) { in X86TargetLowering()
819 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) { in X86TargetLowering()
2527 if (!Subtarget.is64Bit() && !Subtarget.hasX87()) { in getNumRegistersForCallingConv()
2671 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) && in getOptimalMemOpType()
8942 if (Subtarget.hasSSE3() && !Subtarget.hasXOP() && in LowerBuildVectorv4x32()
10809 if (Subtarget.hasVLX() && Subtarget.hasBWI()) in createVariablePermute()
10844 if (Subtarget.hasVLX() && Subtarget.hasVBMI()) in createVariablePermute()
10878 if (Subtarget.hasVLX() && Subtarget.hasBWI()) in createVariablePermute()
20982 if (Subtarget.hasDQI() && Subtarget.hasVLX() && in isLegalConversion()
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H A DX86FastISel.cpp50 const X86Subtarget *Subtarget; member in __anon47f1d02c0111::X86FastISel
1934 if (!Subtarget->is64Bit()) in X86SelectDivRem()
2030 if (!Subtarget->canUseCMOV()) in X86FastEmitCMoveSelect()
2201 if (Subtarget->hasAVX512()) { in X86FastEmitSSESelect()
2594 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) in fastLowerIntrinsicCall()
2793 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
2974 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
2980 if (!Subtarget->hasSSE2()) in fastLowerIntrinsicCall()
3053 if (!Subtarget->is64Bit()) in fastLowerArguments()
3139 if (Subtarget->is64Bit()) in computeBytesPoppedByCalleeForSRet()
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H A DX86LoadValueInjectionRetHardening.cpp63 const X86Subtarget *Subtarget = &MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
64 if (!Subtarget->useLVIControlFlowIntegrity() || !Subtarget->is64Bit()) in runOnMachineFunction()
73 const X86RegisterInfo *TRI = Subtarget->getRegisterInfo(); in runOnMachineFunction()
74 const X86InstrInfo *TII = Subtarget->getInstrInfo(); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp27 const CSKYSubtarget *Subtarget; member in __anon98fb03c10111::CSKYDAGToDAGISel
38 Subtarget = &MF.getSubtarget<CSKYSubtarget>(); in runOnMachineFunction()
80 Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF); in Select()
279 if (!Subtarget->hasFPUv2DoubleFloat()) in selectBITCAST_TO_LOHI()
304 Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1); in selectAddCarry()
310 Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1); in selectAddCarry()
315 NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::ADDC32 in selectAddCarry()
323 static SDValue InvertCarryFlag(const CSKYSubtarget *Subtarget, in InvertCarryFlag() argument
347 Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1); in selectSubCarry()
353 Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1); in selectSubCarry()
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H A DCSKY.td37 def HasFdivdu : Predicate<"Subtarget->hasFdivdu()">,
107 def HasSTM : Predicate<"Subtarget->hasSTM()">,
119 def HasDSP : Predicate<"Subtarget->hasDSP()">,
169 def HasJAVA : Predicate<"Subtarget->hasJAVA()">,
181 def HasNVIC : Predicate<"Subtarget->hasNVIC()">,
255 def UseCCRT : Predicate<"Subtarget->useCCRT()">,
268 def iHasE1 : Predicate<"Subtarget->hasE1()">,
275 def iHasE2 : Predicate<"Subtarget->hasE2()">,
281 def iHas2E3 : Predicate<"Subtarget->has2E3()">,
287 def iHasMP : Predicate<"Subtarget->hasMP()">,
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/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp56 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
67 if (!Subtarget.is64Bit()) in getReservedRegs()
82 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
90 if (!Subtarget.isV9()) { in getReservedRegs()
107 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
108 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
173 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
182 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
184 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
196 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp79 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getRegAllocationHints() local
80 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in getRegAllocationHints()
193 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
194 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_SaveList in getCalleeSavedRegs()
200 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
204 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList in getCalleeSavedRegs()
216 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
217 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_RegMask in getCallPreservedMask()
224 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
228 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask in getCallPreservedMask()
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/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp39 MVT GRLenVT = Subtarget.getGRLenVT(); in LoongArchTargetLowering()
42 if (Subtarget.hasBasicF()) in LoongArchTargetLowering()
44 if (Subtarget.hasBasicD()) in LoongArchTargetLowering()
58 if (Subtarget.is64Bit()) { in LoongArchTargetLowering()
64 if (Subtarget.hasBasicF() && !Subtarget.hasBasicD()) in LoongArchTargetLowering()
71 if (Subtarget.hasBasicF()) { in LoongArchTargetLowering()
75 if (Subtarget.hasBasicD()) { in LoongArchTargetLowering()
86 if (!Subtarget.is64Bit()) in LoongArchTargetLowering()
167 Subtarget.is64Bit() && Subtarget.hasBasicF()) { in lowerBITCAST()
180 !Subtarget.hasBasicD()) { in lowerFP_TO_SINT()
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H A DLoongArch.td21 : Predicate<"Subtarget->is64Bit()">,
25 : Predicate<"!Subtarget->is64Bit()">,
37 : Predicate<"Subtarget->hasBasicF()">,
47 : Predicate<"Subtarget->hasBasicD()">,
56 : Predicate<"Subtarget->hasExtLSX()">,
66 : Predicate<"Subtarget->hasExtLASX()">,
75 : Predicate<"Subtarget->hasExtLVZ()">,
84 : Predicate<"Subtarget->hasExtLBT()">,

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