37     : TargetLowering(TM), Subtarget(STI) {  in LoongArchTargetLowering()
39   MVT GRLenVT = Subtarget.getGRLenVT();  in LoongArchTargetLowering()
42   if (Subtarget.hasBasicF())  in LoongArchTargetLowering()
44   if (Subtarget.hasBasicD())  in LoongArchTargetLowering()
58   if (Subtarget.is64Bit()) {  in LoongArchTargetLowering()
64     if (Subtarget.hasBasicF() && !Subtarget.hasBasicD())  in LoongArchTargetLowering()
71   if (Subtarget.hasBasicF()) {  in LoongArchTargetLowering()
75   if (Subtarget.hasBasicD()) {  in LoongArchTargetLowering()
86   if (!Subtarget.is64Bit())  in LoongArchTargetLowering()
99   setMaxAtomicSizeInBitsSupported(Subtarget.getGRLen());  in LoongArchTargetLowering()
127     assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() &&  in LowerOperation()
167       Subtarget.is64Bit() && Subtarget.hasBasicF()) {  in lowerBITCAST()
179   if (Op.getValueSizeInBits() > 32 && Subtarget.hasBasicF() &&  in lowerFP_TO_SINT()
180       !Subtarget.hasBasicD()) {  in lowerFP_TO_SINT()
204     SDValue Addr(DAG.getMachineNode(Subtarget.is64Bit() ? LoongArch::ADDI_D  in lowerConstantPool()
218   unsigned ADDIOp = Subtarget.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;  in lowerGlobalAddress()
247   SDValue MinusGRLen = DAG.getConstant(-(int)Subtarget.getGRLen(), DL, VT);  in lowerShiftLeftParts()
248   SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);  in lowerShiftLeftParts()
298   SDValue MinusGRLen = DAG.getConstant(-(int)Subtarget.getGRLen(), DL, VT);  in lowerShiftRightParts()
299   SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);  in lowerShiftRightParts()
362     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&  in ReplaceNodeResults()
370     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&  in ReplaceNodeResults()
382     if (VT == MVT::i32 && SrcVT == MVT::f32 && Subtarget.is64Bit() &&  in ReplaceNodeResults()
383         Subtarget.hasBasicF()) {  in ReplaceNodeResults()
391     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&  in ReplaceNodeResults()
404                                  const LoongArchSubtarget &Subtarget) {  in performANDCombine()  argument
417   MVT GRLenVT = Subtarget.getGRLenVT();  in performANDCombine()
467                                  const LoongArchSubtarget &Subtarget) {  in performSRLCombine()  argument
481   MVT GRLenVT = Subtarget.getGRLenVT();  in performSRLCombine()
508                                 const LoongArchSubtarget &Subtarget) {  in performORCombine()  argument
509   MVT GRLenVT = Subtarget.getGRLenVT();  in performORCombine()
731     return performANDCombine(N, DAG, DCI, Subtarget);  in PerformDAGCombine()
733     return performORCombine(N, DAG, DCI, Subtarget);  in PerformDAGCombine()
735     return performSRLCombine(N, DAG, DCI, Subtarget);  in PerformDAGCombine()
783     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo());  in EmitInstrWithCustomInserter()
1003   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();  in LowerCall()
1094   if (VT == MVT::f32 && !Subtarget.hasBasicF())  in isFPImmLegal()
1096   if (VT == MVT::f64 && !Subtarget.hasBasicD())  in isFPImmLegal()