Lines Matching refs:Subtarget
52 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemset()
90 if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned in EmitTargetCodeForMemset()
123 bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in EmitTargetCodeForMemset()
155 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovs() argument
158 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepmovs()
177 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovsB() argument
180 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitRepmovsB()
185 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, in getOptimalRepmovsType() argument
197 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in getOptimalRepmovsType()
206 SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl, in emitConstantSizeRepmov() argument
213 if (!AlwaysInline && Size > Subtarget.getMaxInlineSizeThreshold()) in emitConstantSizeRepmov()
217 if (Subtarget.hasERMSB()) in emitConstantSizeRepmov()
218 return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size); in emitConstantSizeRepmov()
220 assert(!Subtarget.hasERMSB() && "No efficient RepMovs"); in emitConstantSizeRepmov()
226 const MVT BlockType = getOptimalRepmovsType(Subtarget, Align); in emitConstantSizeRepmov()
231 emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitConstantSizeRepmov()
243 return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size); in emitConstantSizeRepmov()
276 const X86Subtarget &Subtarget = in EmitTargetCodeForMemcpy() local
280 if (UseFSRMForMemcpy && Subtarget.hasFSRM()) in EmitTargetCodeForMemcpy()
281 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, Size, MVT::i8); in EmitTargetCodeForMemcpy()
286 DAG, Subtarget, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), in EmitTargetCodeForMemcpy()