Lines Matching refs:Subtarget
50 : TargetLowering(TM), Subtarget(STI) { in RISCVTargetLowering()
52 if (Subtarget.isRV32E()) in RISCVTargetLowering()
55 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in RISCVTargetLowering()
59 !Subtarget.hasStdExtF()) { in RISCVTargetLowering()
63 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
65 !Subtarget.hasStdExtD()) { in RISCVTargetLowering()
69 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
84 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering()
89 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
91 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
93 if (Subtarget.hasStdExtD()) in RISCVTargetLowering()
113 if (Subtarget.hasVInstructions()) { in RISCVTargetLowering()
117 unsigned MinElts = RISCV::RVVBitsPerBlock / Subtarget.getELEN(); in RISCVTargetLowering()
141 !Subtarget.hasVInstructionsI64()) in RISCVTargetLowering()
146 if (Subtarget.hasVInstructionsF16()) in RISCVTargetLowering()
150 if (Subtarget.hasVInstructionsF32()) in RISCVTargetLowering()
154 if (Subtarget.hasVInstructionsF64()) in RISCVTargetLowering()
158 if (Subtarget.useRVVForFixedLengthVectors()) { in RISCVTargetLowering()
162 const RISCVRegisterInfo &TRI = *Subtarget.getRegisterInfo(); in RISCVTargetLowering()
200 if (!Subtarget.hasStdExtZbb()) in RISCVTargetLowering()
203 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
218 if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul()) { in RISCVTargetLowering()
221 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
228 if (!Subtarget.hasStdExtM()) { in RISCVTargetLowering()
232 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
245 if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp() || in RISCVTargetLowering()
246 Subtarget.hasStdExtZbkb()) { in RISCVTargetLowering()
247 if (Subtarget.is64Bit()) in RISCVTargetLowering()
253 if (Subtarget.hasStdExtZbp()) { in RISCVTargetLowering()
263 if (Subtarget.is64Bit()) in RISCVTargetLowering()
269 (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) in RISCVTargetLowering()
274 Subtarget.hasStdExtZbkb() ? Custom : Expand); in RISCVTargetLowering()
277 if (Subtarget.hasStdExtZbb()) { in RISCVTargetLowering()
281 if (Subtarget.is64Bit()) in RISCVTargetLowering()
288 if (Subtarget.is64Bit()) in RISCVTargetLowering()
292 if (Subtarget.hasStdExtZbt()) { in RISCVTargetLowering()
296 if (Subtarget.is64Bit()) in RISCVTargetLowering()
319 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
322 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
342 if (Subtarget.is64Bit()) in RISCVTargetLowering()
346 if (Subtarget.hasStdExtF()) { in RISCVTargetLowering()
357 if (Subtarget.hasStdExtF() && Subtarget.is64Bit()) in RISCVTargetLowering()
360 if (Subtarget.hasStdExtD()) { in RISCVTargetLowering()
375 if (Subtarget.is64Bit()) in RISCVTargetLowering()
380 if (Subtarget.hasStdExtF()) { in RISCVTargetLowering()
398 if (Subtarget.is64Bit()) in RISCVTargetLowering()
404 Subtarget.is64Bit() ? Legal : Custom); in RISCVTargetLowering()
408 if (Subtarget.is64Bit()) in RISCVTargetLowering()
411 if (Subtarget.hasStdExtA()) { in RISCVTargetLowering()
412 setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); in RISCVTargetLowering()
420 if (Subtarget.hasVInstructions()) { in RISCVTargetLowering()
429 if (Subtarget.is64Bit()) in RISCVTargetLowering()
470 if (!Subtarget.is64Bit()) { in RISCVTargetLowering()
551 if (VT.getVectorElementType() == MVT::i64 && !Subtarget.hasStdExtV()) in RISCVTargetLowering()
719 if (Subtarget.hasVInstructionsF16()) { in RISCVTargetLowering()
727 if (Subtarget.hasVInstructionsF32()) { in RISCVTargetLowering()
736 if (Subtarget.hasVInstructionsF64()) { in RISCVTargetLowering()
746 if (Subtarget.useRVVForFixedLengthVectors()) { in RISCVTargetLowering()
809 if (!Subtarget.is64Bit() && VT.getVectorElementType() == MVT::i64) { in RISCVTargetLowering()
833 if (VT.getVectorElementType() != MVT::i64 || Subtarget.hasStdExtV()) in RISCVTargetLowering()
922 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
924 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
926 if (Subtarget.hasStdExtD()) in RISCVTargetLowering()
932 const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4); in RISCVTargetLowering()
943 if (Subtarget.is64Bit()) in RISCVTargetLowering()
946 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
949 if (Subtarget.hasStdExtZbp()) in RISCVTargetLowering()
952 if (Subtarget.hasStdExtZbb()) in RISCVTargetLowering()
955 if (Subtarget.hasStdExtZbkb()) in RISCVTargetLowering()
957 if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZbb()) in RISCVTargetLowering()
959 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
962 if (Subtarget.hasVInstructions()) in RISCVTargetLowering()
966 if (Subtarget.useRVVForFixedLengthVectors()) in RISCVTargetLowering()
978 if (Subtarget.hasVInstructions() && in getSetCCResultType()
979 (VT.isScalableVector() || Subtarget.useRVVForFixedLengthVectors())) in getSetCCResultType()
985 return Subtarget.getXLenVT(); in getVPExplicitVectorLengthTy()
1062 if (Subtarget.hasVInstructions() && isa<VectorType>(Ty)) in isLegalAddressingMode()
1095 if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy()) in isTruncateFree()
1103 if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() || in isTruncateFree()
1127 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
1131 return Subtarget.is64Bit() && CI->getType()->isIntegerTy(32); in signExtendConstant()
1135 return Subtarget.hasStdExtZbb(); in isCheapToSpeculateCttz()
1139 return Subtarget.hasStdExtZbb(); in isCheapToSpeculateCtlz()
1149 return (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp() || in hasAndNotCompare()
1150 Subtarget.hasStdExtZbkb()) && in hasAndNotCompare()
1165 if (BitSize > Subtarget.getXLen()) in shouldConvertConstantLoadToIntImm()
1177 if (!Subtarget.enableUnalignedScalarMem()) in shouldConvertConstantLoadToIntImm()
1187 RISCVMatInt::generateInstSeq(Val, Subtarget.getFeatureBits()); in shouldConvertConstantLoadToIntImm()
1188 return Seq.size() <= Subtarget.getMaxBuildIntsCost(); in shouldConvertConstantLoadToIntImm()
1222 if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions()) in shouldSinkOperands()
1347 if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) in isFPImmLegal()
1349 if (VT == MVT::f32 && !Subtarget.hasStdExtF()) in isFPImmLegal()
1351 if (VT == MVT::f64 && !Subtarget.hasStdExtD()) in isFPImmLegal()
1357 return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || in hasBitPreservingFPLogic()
1358 (VT == MVT::f32 && Subtarget.hasStdExtF()) || in hasBitPreservingFPLogic()
1359 (VT == MVT::f64 && Subtarget.hasStdExtD()); in hasBitPreservingFPLogic()
1368 if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) in getRegisterTypeForCallingConv()
1380 if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) in getNumRegistersForCallingConv()
1558 return !Subtarget.useRVVForFixedLengthVectors() || in mergeStoresAfterLegalization()
1571 return Subtarget.hasVInstructionsI64(); in isLegalElementTypeForRVV()
1574 return Subtarget.hasVInstructionsF16(); in isLegalElementTypeForRVV()
1576 return Subtarget.hasVInstructionsF32(); in isLegalElementTypeForRVV()
1578 return Subtarget.hasVInstructionsF64(); in isLegalElementTypeForRVV()
1597 const RISCVSubtarget &Subtarget) { in useRVVForFixedLengthVectorVT() argument
1599 if (!Subtarget.useRVVForFixedLengthVectors()) in useRVVForFixedLengthVectorVT()
1609 unsigned MinVLen = Subtarget.getRealMinVLen(); in useRVVForFixedLengthVectorVT()
1629 if (!Subtarget.hasVInstructionsI64()) in useRVVForFixedLengthVectorVT()
1633 if (!Subtarget.hasVInstructionsF16()) in useRVVForFixedLengthVectorVT()
1637 if (!Subtarget.hasVInstructionsF32()) in useRVVForFixedLengthVectorVT()
1641 if (!Subtarget.hasVInstructionsF64()) in useRVVForFixedLengthVectorVT()
1647 if (EltVT.getSizeInBits() > Subtarget.getELEN()) in useRVVForFixedLengthVectorVT()
1652 if (LMul > Subtarget.getMaxLMULForFixedLengthVectors()) in useRVVForFixedLengthVectorVT()
1664 return ::useRVVForFixedLengthVectorVT(VT, Subtarget); in useRVVForFixedLengthVectorVT()
1669 const RISCVSubtarget &Subtarget) { in getContainerForFixedLengthVector() argument
1672 useRVVForFixedLengthVectorVT(VT, Subtarget)) && in getContainerForFixedLengthVector()
1675 unsigned MinVLen = Subtarget.getRealMinVLen(); in getContainerForFixedLengthVector()
1676 unsigned MaxELen = Subtarget.getELEN(); in getContainerForFixedLengthVector()
1703 const RISCVSubtarget &Subtarget) { in getContainerForFixedLengthVector() argument
1705 Subtarget); in getContainerForFixedLengthVector()
1714 const RISCVSubtarget &Subtarget) { in convertToScalableVector() argument
1720 SDValue Zero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); in convertToScalableVector()
1726 const RISCVSubtarget &Subtarget) { in convertFromScalableVector() argument
1732 SDValue Zero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); in convertFromScalableVector()
1758 const RISCVSubtarget &Subtarget) { in getDefaultVLOps() argument
1760 MVT XLenVT = Subtarget.getXLenVT(); in getDefaultVLOps()
1771 const RISCVSubtarget &Subtarget) { in getDefaultScalableVLOps() argument
1773 return getDefaultVLOps(VecVT, VecVT, DL, DAG, Subtarget); in getDefaultScalableVLOps()
1790 const RISCVSubtarget &Subtarget) { in lowerFP_TO_INT_SAT() argument
1812 DAG.getTargetConstant(RISCVFPRndMode::RTZ, DL, Subtarget.getXLenVT())); in lowerFP_TO_INT_SAT()
2035 const RISCVSubtarget &Subtarget) { in matchSplatAsGather() argument
2046 if (Idx.getValueType() != Subtarget.getXLenVT()) in matchSplatAsGather()
2051 ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); in matchSplatAsGather()
2052 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in matchSplatAsGather()
2056 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in matchSplatAsGather()
2064 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in matchSplatAsGather()
2068 const RISCVSubtarget &Subtarget) { in lowerBUILD_VECTOR() argument
2072 MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); in lowerBUILD_VECTOR()
2076 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerBUILD_VECTOR()
2078 MVT XLenVT = Subtarget.getXLenVT(); in lowerBUILD_VECTOR()
2084 return convertFromScalableVector(VT, VMClr, DAG, Subtarget); in lowerBUILD_VECTOR()
2089 return convertFromScalableVector(VT, VMSet, DAG, Subtarget); in lowerBUILD_VECTOR()
2101 std::min(std::max(NumElts, 8u), Subtarget.getXLen()); in lowerBUILD_VECTOR()
2102 NumViaIntegerBits = std::min(NumViaIntegerBits, Subtarget.getELEN()); in lowerBUILD_VECTOR()
2189 if (auto Gather = matchSplatAsGather(Splat, VT, DL, DAG, Subtarget)) in lowerBUILD_VECTOR()
2195 return convertFromScalableVector(VT, Splat, DAG, Subtarget); in lowerBUILD_VECTOR()
2231 VID = convertFromScalableVector(VT, VID, DAG, Subtarget); in lowerBUILD_VECTOR()
2287 if (Subtarget.is64Bit() && ViaIntVT == MVT::i32) in lowerBUILD_VECTOR()
2294 (!Subtarget.is64Bit() && ViaIntVT == MVT::i64)) && in lowerBUILD_VECTOR()
2300 getContainerForFixedLengthVector(DAG, ViaVecVT, Subtarget); in lowerBUILD_VECTOR()
2305 Splat = convertFromScalableVector(ViaVecVT, Splat, DAG, Subtarget); in lowerBUILD_VECTOR()
2442 const RISCVSubtarget &Subtarget) { in lowerScalarSplat() argument
2453 MVT XLenVT = Subtarget.getXLenVT(); in lowerScalarSplat()
2485 const RISCVSubtarget &Subtarget) { in isInterleaveShuffle() argument
2487 if (VT.getScalarSizeInBits() >= Subtarget.getELEN()) in isInterleaveShuffle()
2600 const RISCVSubtarget &Subtarget) { in lowerVECTOR_SHUFFLE() argument
2604 MVT XLenVT = Subtarget.getXLenVT(); in lowerVECTOR_SHUFFLE()
2609 MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); in lowerVECTOR_SHUFFLE()
2612 std::tie(TrueMask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2655 return convertFromScalableVector(VT, NewLoad, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2677 return convertFromScalableVector(VT, Splat, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2680 V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2685 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2699 LoV = convertToScalableVector(ContainerVT, LoV, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2703 HiV = convertToScalableVector(ContainerVT, HiV, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2727 return convertFromScalableVector(VT, Res, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2733 if (isInterleaveShuffle(Mask, VT, SwapSources, Subtarget)) { in lowerVECTOR_SHUFFLE()
2753 getContainerForFixedLengthVector(DAG, WideIntVT, Subtarget); in lowerVECTOR_SHUFFLE()
2759 V1 = convertToScalableVector(HalfContainerVT, V1, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2760 V2 = convertToScalableVector(HalfContainerVT, V2, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2797 return convertFromScalableVector(VT, Add, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2886 Subtarget); in lowerVECTOR_SHUFFLE()
2888 V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2900 convertToScalableVector(IndexContainerVT, LHSIndices, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2910 V2 = convertToScalableVector(ContainerVT, V2, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2914 convertToScalableVector(MaskContainerVT, SelectMask, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2927 convertToScalableVector(IndexContainerVT, RHSIndices, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2933 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2950 isInterleaveShuffle(M, SVT, SwapSources, Subtarget); in isShuffleMaskLegal()
3065 const RISCVSubtarget &Subtarget) { in lowerConstant() argument
3078 if (!Subtarget.useConstantPoolForLargeInts()) in lowerConstant()
3082 RISCVMatInt::generateInstSeq(Imm, Subtarget.getFeatureBits()); in lowerConstant()
3083 if (Seq.size() <= Subtarget.getMaxBuildIntsCost()) in lowerConstant()
3106 return lowerConstant(Op, DAG, Subtarget); in LowerOperation()
3128 MVT XLenVT = Subtarget.getXLenVT(); in LowerOperation()
3129 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
3134 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
3135 Subtarget.hasStdExtF()) { in LowerOperation()
3194 if (Subtarget.hasStdExtZbp()) { in LowerOperation()
3204 assert(Subtarget.hasStdExtZbkb() && "Unexpected custom legalization"); in LowerOperation()
3216 assert(VT == Subtarget.getXLenVT() && "Unexpected custom legalization"); in LowerOperation()
3221 unsigned ShAmtWidth = Subtarget.getXLen() - 1; in LowerOperation()
3268 if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock) in LowerOperation()
3296 if (Op.getValueType() == MVT::f16 && Subtarget.is64Bit() && in LowerOperation()
3408 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
3410 Src = convertToScalableVector(SrcContainerVT, Src, DAG, Subtarget); in LowerOperation()
3412 return convertFromScalableVector(VT, Src, DAG, Subtarget); in LowerOperation()
3416 return lowerFP_TO_INT_SAT(Op, DAG, Subtarget); in LowerOperation()
3467 return lowerBUILD_VECTOR(Op, DAG, Subtarget); in LowerOperation()
3473 return lowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
3545 assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
3782 MVT XLenVT = Subtarget.getXLenVT(); in getStaticTLSAddr()
3889 MVT XLenVT = Subtarget.getXLenVT(); in lowerSELECT()
3951 MVT XLenVT = Subtarget.getXLenVT(); in lowerBRCOND()
3988 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); in lowerFRAMEADDR()
3993 int XLenInBytes = Subtarget.getXLen() / 8; in lowerFRAMEADDR()
4011 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); in lowerRETURNADDR()
4015 MVT XLenVT = Subtarget.getXLenVT(); in lowerRETURNADDR()
4016 int XLenInBytes = Subtarget.getXLen() / 8; in lowerRETURNADDR()
4056 SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); in lowerShiftLeftParts()
4057 SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); in lowerShiftLeftParts()
4106 SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); in lowerShiftRightParts()
4107 SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); in lowerShiftRightParts()
4139 SDValue VL = getDefaultScalableVLOps(VT, DL, DAG, Subtarget).second; in lowerVectorMaskSplat()
4143 SDValue VL = getDefaultScalableVLOps(VT, DL, DAG, Subtarget).second; in lowerVectorMaskSplat()
4146 MVT XLenVT = Subtarget.getXLenVT(); in lowerVectorMaskSplat()
4165 assert(!Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64 && in lowerSPLAT_VECTOR_PARTS()
4177 getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerSPLAT_VECTOR_PARTS()
4181 return convertFromScalableVector(VecVT, Res, DAG, Subtarget); in lowerSPLAT_VECTOR_PARTS()
4230 SDValue CC = convertToScalableVector(I1ContainerVT, Src, DAG, Subtarget); in lowerVectorMaskExt()
4233 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerVectorMaskExt()
4235 MVT XLenVT = Subtarget.getXLenVT(); in lowerVectorMaskExt()
4246 return convertFromScalableVector(VecVT, Select, DAG, Subtarget); in lowerVectorMaskExt()
4266 convertToScalableVector(ContainerVT, Op.getOperand(0), DAG, Subtarget); in lowerFixedLengthVectorExtendToRVV()
4270 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerFixedLengthVectorExtendToRVV()
4274 return convertFromScalableVector(ExtVT, Ext, DAG, Subtarget); in lowerFixedLengthVectorExtendToRVV()
4300 Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget); in lowerVectorMaskTruncLike()
4304 Mask = convertToScalableVector(MaskContainerVT, Mask, DAG, Subtarget); in lowerVectorMaskTruncLike()
4310 getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerVectorMaskTruncLike()
4313 SDValue SplatOne = DAG.getConstant(1, DL, Subtarget.getXLenVT()); in lowerVectorMaskTruncLike()
4314 SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); in lowerVectorMaskTruncLike()
4327 Trunc = convertFromScalableVector(MaskVT, Trunc, DAG, Subtarget); in lowerVectorMaskTruncLike()
4365 Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget); in lowerVectorTruncLike()
4368 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerVectorTruncLike()
4375 getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget); in lowerVectorTruncLike()
4388 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerVectorTruncLike()
4429 Src = convertToScalableVector(SrcContainerVT, Src, DAG, Subtarget); in lowerVectorFPExtendOrRoundLike()
4432 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerVectorFPExtendOrRoundLike()
4438 getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget); in lowerVectorFPExtendOrRoundLike()
4445 Src = convertFromScalableVector(VT, Src, DAG, Subtarget); in lowerVectorFPExtendOrRoundLike()
4458 return convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerVectorFPExtendOrRoundLike()
4489 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerINSERT_VECTOR_ELT()
4492 MVT XLenVT = Subtarget.getXLenVT(); in lowerINSERT_VECTOR_ELT()
4495 bool IsLegalInsert = Subtarget.is64Bit() || Val.getValueType() != MVT::i64; in lowerINSERT_VECTOR_ELT()
4509 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerINSERT_VECTOR_ELT()
4520 return convertFromScalableVector(VecVT, Vec, DAG, Subtarget); in lowerINSERT_VECTOR_ELT()
4535 getDefaultScalableVLOps(I32ContainerVT, DL, DAG, Subtarget).first; in lowerINSERT_VECTOR_ELT()
4560 return convertFromScalableVector(VecVT, Slideup, DAG, Subtarget); in lowerINSERT_VECTOR_ELT()
4574 MVT XLenVT = Subtarget.getXLenVT(); in lowerEXTRACT_VECTOR_ELT()
4584 unsigned MaxEEW = Subtarget.getELEN(); in lowerEXTRACT_VECTOR_ELT()
4627 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerEXTRACT_VECTOR_ELT()
4652 const RISCVSubtarget &Subtarget) { in lowerVectorIntrinsicScalars() argument
4657 if (!Subtarget.hasVInstructions()) in lowerVectorIntrinsicScalars()
4675 MVT XLenVT = Subtarget.getXLenVT(); in lowerVectorIntrinsicScalars()
4740 unsigned VectorBitsMax = Subtarget.getRealMaxVLen(); in lowerVectorIntrinsicScalars()
4744 unsigned VectorBitsMin = Subtarget.getRealMinVLen(); in lowerVectorIntrinsicScalars()
4841 MVT XLenVT = Subtarget.getXLenVT(); in LowerINTRINSIC_WO_CHAIN()
4903 Subtarget); in LowerINTRINSIC_WO_CHAIN()
4955 return lowerVectorIntrinsicScalars(Op, DAG, Subtarget); in LowerINTRINSIC_WO_CHAIN()
4966 MVT XLenVT = Subtarget.getXLenVT(); in LowerINTRINSIC_W_CHAIN()
4979 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in LowerINTRINSIC_W_CHAIN()
4980 PassThru = convertToScalableVector(ContainerVT, PassThru, DAG, Subtarget); in LowerINTRINSIC_W_CHAIN()
5010 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in LowerINTRINSIC_W_CHAIN()
5028 MVT XLenVT = Subtarget.getXLenVT(); in LowerINTRINSIC_W_CHAIN()
5048 DAG, Subtarget)); in LowerINTRINSIC_W_CHAIN()
5054 return lowerVectorIntrinsicScalars(Op, DAG, Subtarget); in LowerINTRINSIC_W_CHAIN()
5065 MVT XLenVT = Subtarget.getXLenVT(); in LowerINTRINSIC_VOID()
5076 Val = convertToScalableVector(ContainerVT, Val, DAG, Subtarget); in LowerINTRINSIC_VOID()
5079 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in LowerINTRINSIC_VOID()
5151 MVT XLenVT = Subtarget.getXLenVT(); in lowerVectorMaskVecReduction()
5158 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerVectorMaskVecReduction()
5167 getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerVectorMaskVecReduction()
5250 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerVECREDUCE()
5254 MVT XLenVT = Subtarget.getXLenVT(); in lowerVECREDUCE()
5257 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerVECREDUCE()
5263 M1VT, DL, DAG, Subtarget); in lowerVECREDUCE()
5315 VectorVal = convertToScalableVector(ContainerVT, VectorVal, DAG, Subtarget); in lowerFPVECREDUCE()
5319 MVT XLenVT = Subtarget.getXLenVT(); in lowerFPVECREDUCE()
5322 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerFPVECREDUCE()
5326 M1VT, DL, DAG, Subtarget); in lowerFPVECREDUCE()
5382 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerVPREDUCE()
5389 MVT XLenVT = Subtarget.getXLenVT(); in lowerVPREDUCE()
5394 DL, DAG, Subtarget); in lowerVPREDUCE()
5412 MVT XLenVT = Subtarget.getXLenVT(); in lowerINSERT_SUBVECTOR()
5414 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); in lowerINSERT_SUBVECTOR()
5464 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerINSERT_SUBVECTOR()
5470 SubVec = convertFromScalableVector(VecVT, SubVec, DAG, Subtarget); in lowerINSERT_SUBVECTOR()
5474 getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).first; in lowerINSERT_SUBVECTOR()
5483 Slideup = convertFromScalableVector(VecVT, Slideup, DAG, Subtarget); in lowerINSERT_SUBVECTOR()
5533 std::tie(Mask, VL) = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget); in lowerINSERT_SUBVECTOR()
5565 MVT XLenVT = Subtarget.getXLenVT(); in lowerEXTRACT_SUBVECTOR()
5567 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); in lowerEXTRACT_SUBVECTOR()
5619 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerEXTRACT_SUBVECTOR()
5622 getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).first; in lowerEXTRACT_SUBVECTOR()
5667 std::tie(Mask, VL) = getDefaultScalableVLOps(InterSubVT, DL, DAG, Subtarget); in lowerEXTRACT_SUBVECTOR()
5688 MVT XLenVT = Subtarget.getXLenVT(); in lowerSTEP_VECTOR()
5690 std::tie(Mask, VL) = getDefaultScalableVLOps(VT, DL, DAG, Subtarget); in lowerSTEP_VECTOR()
5702 VL, VT, DL, DAG, Subtarget); in lowerSTEP_VECTOR()
5726 unsigned VectorBitsMax = Subtarget.getRealMaxVLen(); in lowerVECTOR_REVERSE()
5764 MVT XLenVT = Subtarget.getXLenVT(); in lowerVECTOR_REVERSE()
5766 std::tie(Mask, VL) = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget); in lowerVECTOR_REVERSE()
5777 !Subtarget.is64Bit() && IntVT.getVectorElementType() == MVT::i64; in lowerVECTOR_REVERSE()
5798 MVT XLenVT = Subtarget.getXLenVT(); in lowerVECTOR_SPLICE()
5840 MVT XLenVT = Subtarget.getXLenVT(); in lowerFixedLengthVectorLoadToRVV()
5858 SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget); in lowerFixedLengthVectorLoadToRVV()
5875 MVT XLenVT = Subtarget.getXLenVT(); in lowerFixedLengthVectorStoreToRVV()
5890 convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget); in lowerFixedLengthVectorStoreToRVV()
5925 MVT XLenVT = Subtarget.getXLenVT(); in lowerMaskedLoad()
5930 PassThru = convertToScalableVector(ContainerVT, PassThru, DAG, Subtarget); in lowerMaskedLoad()
5933 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerMaskedLoad()
5938 VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second; in lowerMaskedLoad()
5961 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerMaskedLoad()
5990 MVT XLenVT = Subtarget.getXLenVT(); in lowerMaskedStore()
5996 Val = convertToScalableVector(ContainerVT, Val, DAG, Subtarget); in lowerMaskedStore()
5999 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerMaskedStore()
6004 VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second; in lowerMaskedStore()
6028 convertToScalableVector(ContainerVT, Op.getOperand(0), DAG, Subtarget); in lowerFixedLengthVectorSetccToRVV()
6030 convertToScalableVector(ContainerVT, Op.getOperand(1), DAG, Subtarget); in lowerFixedLengthVectorSetccToRVV()
6034 DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT()); in lowerFixedLengthVectorSetccToRVV()
6042 return convertFromScalableVector(VT, Cmp, DAG, Subtarget); in lowerFixedLengthVectorSetccToRVV()
6078 X = convertToScalableVector(ContainerVT, X, DAG, Subtarget); in lowerABS()
6081 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerABS()
6085 DAG.getConstant(0, DL, Subtarget.getXLenVT())); in lowerABS()
6091 return convertFromScalableVector(VT, Max, DAG, Subtarget); in lowerABS()
6104 Mag = convertToScalableVector(ContainerVT, Mag, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
6105 Sign = convertToScalableVector(ContainerVT, Sign, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
6108 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
6113 return convertFromScalableVector(VT, CopySign, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
6125 convertToScalableVector(I1ContainerVT, Op.getOperand(0), DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
6127 convertToScalableVector(ContainerVT, Op.getOperand(1), DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
6129 convertToScalableVector(ContainerVT, Op.getOperand(2), DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
6133 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
6138 return convertFromScalableVector(VT, Select, DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
6161 Ops.push_back(convertToScalableVector(ContainerVT, V, DAG, Subtarget)); in lowerToScalableOp()
6166 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerToScalableOp()
6172 return convertFromScalableVector(VT, ScalableRes, DAG, Subtarget); in lowerToScalableOp()
6199 Ops.push_back(convertToScalableVector(ContainerVT, V, DAG, Subtarget)); in lowerVPOp()
6209 return convertFromScalableVector(VT, VPOp, DAG, Subtarget); in lowerVPOp()
6225 Src = convertToScalableVector(SrcVT, Src, DAG, Subtarget); in lowerVPExtMaskOp()
6228 MVT XLenVT = Subtarget.getXLenVT(); in lowerVPExtMaskOp()
6242 return convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerVPExtMaskOp()
6259 Op1 = convertToScalableVector(ContainerVT, Op1, DAG, Subtarget); in lowerVPSetCCMaskOp()
6260 Op2 = convertToScalableVector(ContainerVT, Op2, DAG, Subtarget); in lowerVPSetCCMaskOp()
6321 return convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerVPSetCCMaskOp()
6338 Src = convertToScalableVector(SrcVT, Src, DAG, Subtarget); in lowerVPFPIntConvOp()
6340 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerVPFPIntConvOp()
6359 MVT XLenVT = Subtarget.getXLenVT(); in lowerVPFPIntConvOp()
6427 MVT XLenVT = Subtarget.getXLenVT(); in lowerVPFPIntConvOp()
6454 return convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerVPFPIntConvOp()
6473 Op1 = convertToScalableVector(ContainerVT, Op1, DAG, Subtarget); in lowerLogicVPOp()
6474 Op2 = convertToScalableVector(ContainerVT, Op2, DAG, Subtarget); in lowerLogicVPOp()
6481 return convertFromScalableVector(VT, Val, DAG, Subtarget); in lowerLogicVPOp()
6521 MVT XLenVT = Subtarget.getXLenVT(); in lowerMaskedGather()
6541 Index = convertToScalableVector(IndexVT, Index, DAG, Subtarget); in lowerMaskedGather()
6545 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerMaskedGather()
6546 PassThru = convertToScalableVector(ContainerVT, PassThru, DAG, Subtarget); in lowerMaskedGather()
6551 VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second; in lowerMaskedGather()
6582 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerMaskedGather()
6623 MVT XLenVT = Subtarget.getXLenVT(); in lowerMaskedScatter()
6643 Index = convertToScalableVector(IndexVT, Index, DAG, Subtarget); in lowerMaskedScatter()
6644 Val = convertToScalableVector(ContainerVT, Val, DAG, Subtarget); in lowerMaskedScatter()
6648 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerMaskedScatter()
6653 VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second; in lowerMaskedScatter()
6679 const MVT XLenVT = Subtarget.getXLenVT(); in lowerGET_ROUNDING()
6710 const MVT XLenVT = Subtarget.getXLenVT(); in lowerSET_ROUNDING()
6742 bool isRISCV64 = Subtarget.is64Bit(); in lowerEH_DWARF_CFA()
6845 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
6895 assert(!Subtarget.is64Bit() && in ReplaceNodeResults()
6909 unsigned XLen = Subtarget.getXLen(); in ReplaceNodeResults()
6924 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
6948 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
6955 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
6959 if (N->getOpcode() == ISD::SHL && Subtarget.hasStdExtZbs() && in ReplaceNodeResults()
6984 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
6992 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
7009 Subtarget.is64Bit() && Subtarget.hasStdExtM() && in ReplaceNodeResults()
7030 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
7065 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
7067 if (Subtarget.hasStdExtZbb()) { in ReplaceNodeResults()
7086 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
7117 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
7118 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
7121 } else if (VT == MVT::i32 && Op0VT == MVT::f32 && Subtarget.is64Bit() && in ReplaceNodeResults()
7122 Subtarget.hasStdExtF()) { in ReplaceNodeResults()
7145 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
7146 assert((VT == MVT::i16 || (VT == MVT::i32 && Subtarget.is64Bit())) && in ReplaceNodeResults()
7149 assert((Subtarget.hasStdExtZbp() || in ReplaceNodeResults()
7150 (Subtarget.hasStdExtZbkb() && N->getOpcode() == RISCVISD::GREV && in ReplaceNodeResults()
7165 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
7167 (VT == MVT::i32 && Subtarget.is64Bit())) && in ReplaceNodeResults()
7168 Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); in ReplaceNodeResults()
7183 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
7184 Subtarget.hasStdExtZbt() && "Unexpected custom legalisation"); in ReplaceNodeResults()
7227 assert(!Subtarget.is64Bit() && N->getValueType(0) == MVT::i64 && in ReplaceNodeResults()
7235 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in ReplaceNodeResults()
7238 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
7275 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
7300 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
7316 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
7340 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
7344 Subtarget.getXLenVT(), N->getOperand(1)); in ReplaceNodeResults()
7349 assert(VT == MVT::i64 && !Subtarget.is64Bit() && in ReplaceNodeResults()
7401 SDVTList VTs = DAG.getVTList(Subtarget.getXLenVT(), MVT::Other); in ReplaceNodeResults()
7629 const RISCVSubtarget &Subtarget) { in combineORToGREV() argument
7630 assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson"); in combineORToGREV()
7633 if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { in combineORToGREV()
7655 const RISCVSubtarget &Subtarget) { in combineORToGORC() argument
7656 assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson"); in combineORToGORC()
7659 if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { in combineORToGORC()
7734 const RISCVSubtarget &Subtarget) { in combineORToSHFL() argument
7735 assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson"); in combineORToSHFL()
7738 if (VT != MVT::i32 && VT != Subtarget.getXLenVT()) in combineORToSHFL()
7809 const RISCVSubtarget &Subtarget) { in transformAddShlImm() argument
7811 if (!Subtarget.hasStdExtZba()) in transformAddShlImm()
7816 if (VT.isVector() || VT.getSizeInBits() > Subtarget.getXLen()) in transformAddShlImm()
7863 const RISCVSubtarget &Subtarget) { in combineROTR_ROTL_RORW_ROLW() argument
7873 if (!Subtarget.hasStdExtZbp() || Src.getOpcode() != RISCVISD::GREV) in combineROTR_ROTL_RORW_ROLW()
8034 const RISCVSubtarget &Subtarget) { in transformAddImmMulImm() argument
8037 if (VT.isVector() || VT.getSizeInBits() > Subtarget.getXLen()) in transformAddImmMulImm()
8083 const RISCVSubtarget &Subtarget) { in performADDCombine() argument
8084 if (SDValue V = transformAddImmMulImm(N, DAG, Subtarget)) in performADDCombine()
8086 if (SDValue V = transformAddShlImm(N, DAG, Subtarget)) in performADDCombine()
8104 const RISCVSubtarget &Subtarget) { in performANDCombine() argument
8111 if (Subtarget.is64Bit() && Subtarget.hasStdExtZbs() && in performANDCombine()
8133 const RISCVSubtarget &Subtarget) { in performORCombine() argument
8134 if (Subtarget.hasStdExtZbp()) { in performORCombine()
8135 if (auto GREV = combineORToGREV(SDValue(N, 0), DAG, Subtarget)) in performORCombine()
8137 if (auto GORC = combineORToGORC(SDValue(N, 0), DAG, Subtarget)) in performORCombine()
8139 if (auto SHFL = combineORToSHFL(SDValue(N, 0), DAG, Subtarget)) in performORCombine()
8177 const RISCVSubtarget &Subtarget) { in performSETCCCombine() argument
8183 if (OpVT != MVT::i64 || !Subtarget.is64Bit()) in performSETCCCombine()
8224 const RISCVSubtarget &Subtarget) { in performSIGN_EXTEND_INREGCombine() argument
8246 if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit() && in performSIGN_EXTEND_INREGCombine()
8504 const RISCVSubtarget &Subtarget) { in performFP_TO_INTCombine() argument
8507 MVT XLenVT = Subtarget.getXLenVT(); in performFP_TO_INTCombine()
8522 if (Src.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh()) in performFP_TO_INTCombine()
8551 const RISCVSubtarget &Subtarget) { in performFP_TO_INT_SATCombine() argument
8554 MVT XLenVT = Subtarget.getXLenVT(); in performFP_TO_INT_SATCombine()
8569 if (Src.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh()) in performFP_TO_INT_SATCombine()
8604 const RISCVSubtarget &Subtarget) { in performBITREVERSECombine() argument
8605 assert(Subtarget.hasStdExtZbkb() && "Unexpected extension"); in performBITREVERSECombine()
8612 if (!VT.isScalarInteger() || VT.getSizeInBits() >= Subtarget.getXLen() || in performBITREVERSECombine()
8657 const RISCVSubtarget &Subtarget) { in performSRACombine() argument
8660 if (N->getValueType(0) != MVT::i64 || !Subtarget.is64Bit()) in performSRACombine()
8752 SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { in combine_CC() argument
8760 LHS.getOperand(0).getValueType() == Subtarget.getXLenVT()) { in combine_CC()
8909 return combineROTR_ROTL_RORW_ROLW(N, DAG, Subtarget); in PerformDAGCombine()
9016 return performADDCombine(N, DAG, Subtarget); in PerformDAGCombine()
9020 return performANDCombine(N, DAG, Subtarget); in PerformDAGCombine()
9022 return performORCombine(N, DAG, Subtarget); in PerformDAGCombine()
9034 return performSETCCCombine(N, DAG, Subtarget); in PerformDAGCombine()
9036 return performSIGN_EXTEND_INREGCombine(N, DAG, Subtarget); in PerformDAGCombine()
9041 if (N->getValueType(0) == MVT::i64 && Subtarget.is64Bit()) { in PerformDAGCombine()
9072 if (combine_CC(LHS, RHS, CC, DL, DAG, Subtarget)) in PerformDAGCombine()
9084 if (combine_CC(LHS, RHS, CC, DL, DAG, Subtarget)) in PerformDAGCombine()
9091 return performBITREVERSECombine(N, DAG, Subtarget); in PerformDAGCombine()
9094 return performFP_TO_INTCombine(N, DCI, Subtarget); in PerformDAGCombine()
9097 return performFP_TO_INT_SATCombine(N, DCI, Subtarget); in PerformDAGCombine()
9144 MVT XLenVT = Subtarget.getXLenVT(); in PerformDAGCombine()
9219 if (SDValue V = performSRACombine(N, DAG, Subtarget)) in PerformDAGCombine()
9231 DAG.getRegister(RISCV::X0, Subtarget.getXLenVT())); in PerformDAGCombine()
9302 DAG.getConstant(1, DL, Subtarget.getXLenVT()), MemVT, in PerformDAGCombine()
9316 DAG, Subtarget)) in PerformDAGCombine()
9358 assert(Subtarget.useRVVForFixedLengthVectors()); in PerformDAGCombine()
9419 Subtarget.getFeatureBits(), in isDesirableToCommuteWithShift()
9422 ShiftedC1Int, Ty.getSizeInBits(), Subtarget.getFeatureBits(), in isDesirableToCommuteWithShift()
9484 if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) { in targetShrinkDemandedConstant()
9619 const unsigned MinVLenB = Subtarget.getRealMinVLen() / 8; in computeKnownBitsForTargetNode()
9620 const unsigned MaxVLenB = Subtarget.getRealMaxVLen() / 8; in computeKnownBitsForTargetNode()
9711 unsigned XLen = Subtarget.getXLen(); in ComputeNumSignBitsForTargetNode()
9911 const RISCVSubtarget &Subtarget) { in emitQuietFCMP() argument
9948 const RISCVSubtarget &Subtarget) { in EmitLoweredCascadedSelect() argument
9984 const RISCVInstrInfo &TII = *Subtarget.getInstrInfo(); in EmitLoweredCascadedSelect()
10050 const RISCVSubtarget &Subtarget) { in emitSelectPseudo() argument
10093 return EmitLoweredCascadedSelect(MI, *Next, BB, Subtarget); in emitSelectPseudo()
10121 const RISCVInstrInfo &TII = *Subtarget.getInstrInfo(); in emitSelectPseudo()
10188 assert(!Subtarget.is64Bit() && in EmitInstrWithCustomInserter()
10195 return emitSelectPseudo(MI, BB, Subtarget); in EmitInstrWithCustomInserter()
10201 return emitQuietFCMP(MI, BB, RISCV::FLE_H, RISCV::FEQ_H, Subtarget); in EmitInstrWithCustomInserter()
10203 return emitQuietFCMP(MI, BB, RISCV::FLT_H, RISCV::FEQ_H, Subtarget); in EmitInstrWithCustomInserter()
10205 return emitQuietFCMP(MI, BB, RISCV::FLE_S, RISCV::FEQ_S, Subtarget); in EmitInstrWithCustomInserter()
10207 return emitQuietFCMP(MI, BB, RISCV::FLT_S, RISCV::FEQ_S, Subtarget); in EmitInstrWithCustomInserter()
10209 return emitQuietFCMP(MI, BB, RISCV::FLE_D, RISCV::FEQ_D, Subtarget); in EmitInstrWithCustomInserter()
10211 return emitQuietFCMP(MI, BB, RISCV::FLT_D, RISCV::FEQ_D, Subtarget); in EmitInstrWithCustomInserter()
10579 if (Subtarget.hasVInstructions()) in analyzeInputArgs()
10610 if (Subtarget.hasVInstructions()) in analyzeOutputArgs()
10633 const RISCVSubtarget &Subtarget) { in convertLocVTToValVT() argument
10639 Val = convertFromScalableVector(VA.getValVT(), Val, DAG, Subtarget); in convertLocVTToValVT()
10675 const RISCVSubtarget &Subtarget) { in convertValVTToLocVT() argument
10683 Val = convertToScalableVector(LocVT, Val, DAG, Subtarget); in convertValVTToLocVT()
10955 MVT XLenVT = Subtarget.getXLenVT(); in LowerFormalArguments()
10956 unsigned XLenInBytes = Subtarget.getXLen() / 8; in LowerFormalArguments()
11130 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); in isEligibleForTailCallOptimization()
11168 MVT XLenVT = Subtarget.getXLenVT(); in LowerCall()
11311 ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL, Subtarget); in LowerCall()
11394 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in LowerCall()
11447 RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL, Subtarget); in LowerCall()
11462 if (Subtarget.hasVInstructions()) in CanLowerReturn()
11533 Val = convertValVTToLocVT(DAG, Val, VA, DL, Subtarget); in LowerReturn()
11803 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) in getRegForInlineAsmConstraint()
11805 if (Subtarget.hasStdExtF() && VT == MVT::f32) in getRegForInlineAsmConstraint()
11807 if (Subtarget.hasStdExtD() && VT == MVT::f64) in getRegForInlineAsmConstraint()
11872 if (Subtarget.hasStdExtF()) { in getRegForInlineAsmConstraint()
11909 if (Subtarget.hasStdExtD() && (VT == MVT::f64 || VT == MVT::Other)) { in getRegForInlineAsmConstraint()
11916 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) { in getRegForInlineAsmConstraint()
11924 if (Subtarget.hasVInstructions()) { in getRegForInlineAsmConstraint()
12015 DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT())); in LowerAsmOperandForConstraint()
12023 DAG.getTargetConstant(0, SDLoc(Op), Subtarget.getXLenVT())); in LowerAsmOperandForConstraint()
12031 DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT())); in LowerAsmOperandForConstraint()
12136 unsigned XLen = Subtarget.getXLen(); in emitMaskedAtomicRMWIntrinsic()
12188 unsigned XLen = Subtarget.getXLen(); in emitMaskedAtomicCmpXchgIntrinsic()
12219 return Subtarget.hasStdExtZfh(); in shouldConvertFpToSat()
12221 return Subtarget.hasStdExtF(); in shouldConvertFpToSat()
12223 return Subtarget.hasStdExtD(); in shouldConvertFpToSat()
12232 if (Subtarget.is64Bit() && !isPositionIndependent() && in getJumpTableEncoding()
12242 assert(Subtarget.is64Bit() && !isPositionIndependent() && in LowerCustomJumpTableEntry()
12253 assert(Subtarget.getRealMinVLen() >= 64 && "zve32* unsupported"); in isVScaleKnownToBeAPowerOfTwo()
12268 return Subtarget.hasStdExtZfh(); in isFMAFasterThanFMulAndFAdd()
12270 return Subtarget.hasStdExtF(); in isFMAFasterThanFMulAndFAdd()
12272 return Subtarget.hasStdExtD(); in isFMAFasterThanFMulAndFAdd()
12293 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in shouldExtendTypeInLibCall()
12301 if (Subtarget.is64Bit() && Type == MVT::i32) in shouldSignExtendTypeInLibCall()
12311 Subtarget.hasStdExtM() || Subtarget.hasStdExtZmmul(); in decomposeMulByConstant()
12315 if (HasExtMOrZmmul && VT.getSizeInBits() > Subtarget.getXLen()) in decomposeMulByConstant()
12324 if (Subtarget.hasStdExtZba() && !Imm.isSignedIntN(12) && in decomposeMulByConstant()
12330 if (HasExtMOrZmmul && VT.getSizeInBits() >= Subtarget.getXLen()) in decomposeMulByConstant()
12354 if (VT.getScalarSizeInBits() > Subtarget.getXLen()) in isMulAddWithConstProfitable()
12375 return Subtarget.enableUnalignedScalarMem(); in allowsMisalignedMemoryAccesses()
12500 if (!Subtarget.hasStdExtZbt()) in BuildSDIVPow2()
12512 if (VT != MVT::i32 && !(Subtarget.is64Bit() && VT == MVT::i64)) in BuildSDIVPow2()
12554 BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF); in getRegisterByName()
12555 if (!ReservedRegs.test(Reg) && !Subtarget.isRegisterReservedByUser(Reg)) in getRegisterByName()